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Re: Handshaking vs FIFO
Hii,
The performance of the system when using HANDSHAKING will be less as the Tx will send the next data only after receiving the acknowledgement from the Rx for the previous data . In this case , there will be synchronizers used for the request(Tx to Rx) and ack...
Re: synchronizers
Hii ,
I have been regularly collecting the papers and information on the synchronizers and Clock Domain Crossing (CDC) and here I want to put all the information which I have collected till now. It includes a lot of very gud papers on CDC and PPTs. Any one who wants, they can...
Hii,
How we can realize the modulo function (%) , which will give the remainder after the division ?
Try for both the combinational and sequential circuits.
thanx,
subbu.
Hii, thanx for the response !!!
Let us say my design is not a latch based design and I am goin to use only one edge either +ve or -ve. In this case , Can I use any other duty cycle clock ? I can definetely use, but whether, are there any conditions which we have to consider for how much duty...
Hii Friends ,
Why we need 50% duty cycle clocks ?? Can't we use some other duty cycle value ?? What are the advantages of using 50% duty cycle waveform ?
thanx,
subbu.
Re: Hi all
There are also combinational shifters like barrel shifters.
The question of sequential or combinational depend on the type of the hardware elements u are using. If you use any memory elements like FLIPFLOPS or latches then that is sequential.
Re: clock synthesization
Before answering u , i want to suggest you one thing. Whenever you are writing the code make sure that what hardware you are expecting for your code from the synthesis tool .
You said you want to change the state on both edges of the clock (I wonder ??) and ur code is...
Re: FLIPFLOP...
What about the output of the flop ??? when the clk edge occurs , which input value it has to take ( u said 2 inputs ) ?? if there is a single output , then there should be a comb at the input which selects one of the two inputs , in which case u can code it using normal flop...
fifo depth calculation cummings
One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation. So size of...
""Writing Testbenches: Functional Verification of HDL Models"" by janick bergeron is the best book. u can get the softcopy of this book in this site. search for it in ebooks upload/download.
Here i have attached some information on writing testbenches , go through it.
subbu
Hii ,
Is it really needed a FIFO while synchronizing a slow clock to a fast clock ??If it is fast to slow u should have a FIFO as we have to store the data. What about slow to fast case ?? As any way there is no need to have more than 1 or 2 locations in the FIFO as fast clock can read data...
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