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I am modeling digital steering DAC in Cadence AMS with spectre. I have extracted current cell, When I modeling it with spectre output current is set in 3ns. I mean delta Iout < 1/2LSB when 111111111111111 turn to 111111111111111 . But when I modeling same via AMS it does not set even in 200ns...
[server@ServDC serverxnor]$ oa2cdb -lib factoryhome -cdslibpath /home/server/PDK/lib.defs
*WARNING* envGetVal: Could not find variable 'dbStatCacheOn'
in tool[.partition] 'cdba'.
*WARNING* envGetVal: Could not find variable 'dbInstNamingGlobalInc'
in tool[.partition] 'cdba'...
I have a schematic with two VDC.
I want to variate their voltage from 0 to 5V and see the output.
I launch ADE, go to variables/edit. Add variable alta with value 0V, altb with same value.
Then I go to Tools/parametric Analysis.
What I need to do?
I do not know Verilog A. I will learn this. But now I need pulse clock generator.
I want to set rise time, fall time, period time, delay time, start signal time, stop time, count of pulses in my symbol, amplitude (Volts),
Where can I find ready examples of that? Surely these must be.
How to realize signal in schematic such on picture on Cadence 5?
I need "ladder" from 0V to -2.04V with step 0.008 V (step can be smaller), 256 time intervaks.
**broken link removed**
1) When I try to short pins such as vdda! with pin created by me I see errors.
2) Also When I try to short pins vdda with vdde I see errors.What the problem?
3) How create global pins in schematic without making that on symbol? I need to use pins with same names in upper scheme of ierarchy...
I have Cadence 5 and 6 installed on Linux. That runs slow!
These is for schematic and editor of topology, not calculation in simulation.
System: OpenSuse 11.1x86-64, Gnome, ATI X1650Pro with Drivers installed.
CPU: Core-5 750, Before this: - Core2 Duo E4400 (also runs slow)
I try another OS -...
error(s) found during netlisting cadence
pvvikas
Are you fix netlist?
You may try to write in view field words such "schematic", "symbol", etc.
It depends on type of the editor.
I have an project (invert).
I have added basic library to this.
I put VSRC from basic lib to scheme
**broken link removed**
When I try to simulate this message appears.
**broken link removed**
How can I solve this problem?
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