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Recent content by strangesiva

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    AVS interface - PowerWise Interface

    Hi , for the communication between the power controller and the external energy management unit a interface protocol called PowerWise Interface is used. Where can i find the specifications for that interface ? its from Texas instruments. If the protocol is outdated . what is the interface...
  2. S

    verilog mod3 counter query on assign statements

    I was simulating the above code in xilinx ise and modelsim . I wanted to know how it happens so i posted this thread . Ok if you mention about the skew factor , in reality how are the reset signals to mod counters realised ? Thanks
  3. S

    verilog mod3 counter query on assign statements

    Hi , the below code uses dff for mod3 counter design . rst generated (using expression1) does not work,where as rst generated (using expression 2) works . what is the reason ? module dff(output reg q,output qn,input d,clk,reset); always @(posedge clk or negedge reset) begin if(!reset) q<=1'b0...
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    leakage currents in cmos inverter

    Hi , Can you please exlain me where the reverse biased diode leakage occurs and please give me an explanation about the path of the reverse current ,as to how it flows and when the leakage stops . And similarly please explain me about sub treshold leakage current too
  5. S

    leakage currents in cmos inverter.

    Hi , Can you please exlain me where the reverse biased diode leakage occurs and please give me an explanation about the path of the reverse current ,as to how it flows and when the leakage stops . And similarly please explain me about sub treshold leakage current too
  6. S

    please explain what is average power ?

    hi, In vlsi design what is the average power ? how is it calculated.
  7. S

    time based power analysis

    what is meant by time based power or power/time ? what happens in time based power analysis. can you please explain time based power with example.
  8. S

    average power analysis

    what is meant by average power ? what happens in average power analysis. can you please explain average power with example.
  9. S

    Explain about peak power analysis ...

    can you please give me the link to that manual. I am not able to find it. It wil be very helpful if u provide it . :)
  10. S

    Explain about peak power analysis ...

    Hi, Thank you so much. I am performing at rtl level. i wanna know what happens is time based power analysis .. can you please tell what happens in elaboration phase also ? pls explain about time based power analysis at rtl level . thanks in advance - - - Updated - - - Hi, Thank you so much. I...
  11. S

    Explain about peak power analysis ...

    Hi, I am interested in power estimation. Iwanna know about peak power analysis or time based power analysis. please tell me what is done in peak analysis.?
  12. S

    resistor and voltages

    Hi , i wanna know what will be the voltage across a resistor it two different power supplies are connected to it parallely ,say 6v is caonnected to R1 in parallel and a 2v is connected to R2 in parallel? what is the voltage across resistor ? explain.
  13. S

    Need help with apache power artist tool

    Hi, I am using power artist tool for the past 2 weeks. I want to know wat happens in various phases. please explain me abt elaboration process and time based power analysis. And i wanna know what is the pthdl and ptshell and pttbengine do?
  14. S

    FSDB- need help about fsdb

    What does fsdb stand for ? and please explain me what details it provides ? and its advantages and shortcomings

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