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astro 2004.06 lab
Could somebody share teh Astro 2004.06 lab data?
I know the 2007.03 can be downloaded from solvnet, but I need 2004.06
Thanks and really really appreciated.
Re: question
true.
there is an official name for this kind of logic alled "canonical signed digit".
that is, for this kind of "constant * variable", you can pretty much convert this form into a series of adder and substractor instead of using an multiplier. For certain types of constants, it...
Re: how to tranfer a pulse from a clock domain to another cl
this is a very practical and useful logic.
Let's say, you want to transfer a pulse in clock domain A (clka) into another pulse in clock domain B (clkb).
First, you make a "toggle" signal in clock domain A. That is, whenever there is...
verilog 2001.
for example, if you have a 4 bit value, lt's say, x=1111 (in binary)
if you use $signed(x), it will be -1
if you use $unsigned(x), it will be f in hex (15 in decimal)
Thanks guys.
However, I don't think the problem is that easy.
Basically, a lot of times, a board can have certain frequency in. For example, 20MHz.
Inside the first FPGA, there's advanced DCM to make the clock higher frequency, let's say, 80MHz.
Now the problem is, if we want to pass this...
Suppose we need a design with clk in one FPGA, and we also need this clk to go to 2nd fpga, and the skew between them must be small.
What's the best way to achieve this?
Thanks
another use is to have #1 delay so that the waveform display is easier to read.
but usually an experienced designer won't be confused by 0 delay waveform.
frontend vs backend semiconductor
i'd recommend you go with frontend first. the reason is, once you get into the backend world, it's hard to get out. No company is going to hire a backend guy to do the frontend design. But uh...if you are a talented frontend designer and you always have the...
ikru26,
I don't think your comments is correct.
Chipscope is sort like a logic analyzer. The most inconvenient part is that you will have to re-compile your design, and sometimes it breaks the timing. Other than that, chipscope behaves just like a logic analyzer. You don't actually need a...
Re: What to do if post layout timing not matching to synthes
It's pretty common to have synthesis pass while failing on post layout timing.
Re-synthesis with higher margin, work with backend team by giving them more information on the floorplan, ....
tcl now becomes the standard "command line interface" language for most eda tools, not only for backend, but also for frontend tools.
Perl is more convenient in handling txt and automation. for example, some people uses perl to do ECO (some people use TCL, but through some eda tools' help of...
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