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debugging timing problems vhdl xilinx
First of all, I know nothing about VHDL, but it seems that your goal is to make the LED blink every one second. For a 25MHz clock frequency, you approximately need a 25-bit register to sequentially count, and connect the MSB to port LED. The report timing...
did the tool show any error message before it halted?
go discuss this problem with personnel of your EDA support/management department...maybe it's ncsim's own problem (not so well installed or configured)...
good luck!
stan
Re: FPGA Design
if the timing issue is not so concerned (you can easily meet the timing constraints of your design)... you can just let the tools do all the job...(synthesis -> synplify pro, P&R -> ISE) Almost automatic!
if the timing is pretty tied or fails to meet the requirements, there's...
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