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Recent content by srp

  1. S

    vlsi training(back end)

    hi, looking for vlsi training(back end) in sacramento/bay-area. pl can you reply if you know anybody who conducts such trainings Thanks!
  2. S

    Differences between the layout in Custom Design and Semi-Custom Design

    Re: LAYOUT guys.... full-custom: you have all the flexibility to create your own structures and polygons in the layout. example :standard cell semi-custom: there are some preplaced structures in the layout; you have limited flexibity to add and remove structures. Example: sea-of-gates
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    Problem with lvs netlist in Cadence as components are not identified

    Re: lvs netlist do you want a flat or a heirarchial netlist?. if you want a flat netlist to see all the components you need to make sure the "flat" is checked.
  4. S

    How to improve the area power and delay of standard cells?

    Re: Layout of standard Cell is your question only on the circuit design or do you wnat to know the physical esign aspect too....
  5. S

    what is strap ? request for resources

    Re: what is strap ? are you asking about contact strap? can you elaborate the context of your questions?
  6. S

    Which verification tool is available for free?

    Re: Verification Tool if you are loking for some free layout tools and also be able to run verification you can use ledit
  7. S

    What is the difference between Macro & Standard Cell?

    Re: Macro & Std Cell Macro is block....for example memories are referred to as hard macros...in other words clusters of cells bound together in a predefined area. Macro can be built a number of standard cell. Standardcell is like an individual building block; you can use any number of these...
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    Core Filler & Metal Filler

    based on my experience......following are the answers 1) core filler cells: Sometimes in std cell layout there are no taps' to make up to that there are filler cells which have taps in them. These are inserted in the rows based on the design rule requirements. 2) Metal filler cells: Sometimes...
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    Why Layout have more ports than source when doing LVS?

    it is possible something might have been renamed by mistake in your layout or if it was disconnected...usually in layout this happens when you open in edit mode ....just some manual mistakes. The LVS is accurate ...if its reporting some mismatch then ...there is definetly something not right...
  10. S

    please help understanding load and slope in .lib

    Hello, Please can someone help me understand the what is load and slope in .lib and also the load matrix. Thanks!
  11. S

    request help on basic design compiler interview questions

    compiler interview questions Hi, Please can somebody help on what kind of basic design compiler questions to expect on an interview. Appreciate your help! Sincerely, Shubha
  12. S

    thickness of gate oxide

    what is the impact on the device performance as the thickness of gate oxide increases or decreases. Thanks!
  13. S

    wiretrack information in ICC

    what does it mean when one refers to wiretrack information in ICC? Thanks!
  14. S

    Where do the DRCs come from?

    DRC drc basically are checks to make sure that every layer is honoring rules that apply to itself as well as the layers that it intersects with.

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