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Hold Time
Does decreasing frequency helps to fix hold-time?
Certainly not. We all know that
Thold <= Tdata-min + Tc-q + (-) Tskew
Here Frequency is determined by Critical path delay (i.e., Tdata-max). So it happens that hold is skrewed by the fastest data which arrives in the next clock pulse...
modelsim spef
spef is a layout extracted file. It have RC values for all the nets.
The syntax is
*NAME_MAP
< mapping of net name to number is done here>
*PORTS
*D_NET <net number> <cap value>
*CONN
<all connections of the net>
*CAP
<cap values>
*RES
<resistance values>
*END
back annotate
While you do timing verification in STA tools before doing actual routing you will estimate the wire delay by wire-load models. But before time closing the entire design (ie., after routing) you will be giving the extracted wire delay models in the format of spef or dspf or some...
you are right. setup is fixed before cts i.e., in placement stage where clock path is ideal. thats y we cannot fix hold. but hold is fixed after cts but before routing. after routing we cannot insert hold buffers.
Re: frequency?????
There will be one functional clock in ur design which is used by most of your design. It may be the fastest clock (not all times). If u still have more then one clock in functional mode u have to ask the front end designer which is the master clock.
Level shifters are used when the signals goes to one voltage domain to another voltage domain. This LS will amplify the signal for that power domain so that the high Voltage domain cells can read logic-1 or logic-0 correctly. Usually LS are inserted only while crossing low voltage domain to high...
level shifter asic
May be during ur RTL coding u can insert them as a macro to your design.
we can also put level shifter during floor plan (during specifying power domain) stage if u have failed to put it during RTL coding or synthesis.
There are several stages for ECO. First if in ur design only there is eco routing. This is metal eco. All P&R tools support this. u can do this by using manual routing. The next one in ur netlist only few combo changes. There u have to do eco placement followed by routing. If there is change in...
Re: DRV
Generally for max-tran violations buffers are added after the gate which screws up the slew. max-cap violation is generally caused when the load is more. it is solved by inserting tree of buffers so that each buffer can handle balanced load. This is the method I know. If there is some...
I like to add one more point to this. This GDSII layer number is given by the foundry. In your tech file a seperate sub-class named streamLayers is there. It defines your layer mapping.
Re: setup margin
Usually setup margin is given for tolerating the difference seen in P&R tool and STA tool. This is like introducing some pessimism in P&R tool so that we can close the design with some 100ps setup or hold margin.
Regarding timing it means we are closing the design with less...
Hey man,
u cannot do everything in gui or just type command by command to work when some command takes hours and hours to execute. Also when u query on a huge MB of log file u have no other choice then to use scripting languages. The are other languages like awk, sed etc... also which server...
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