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I am currently designing a Dual Slope ADC for a very low frequency biomedical system (100Hz input signal sampled up to a max frequency of 10Khz). The overall system has a lot of switches which open and close depending on the integration/reset/discharge cycles. I want to know how I can...
Thank you for the reply. For the inputs to the ADC I am using analog IO. I thought that since the outputs are digital signals I should use digital pads.Also, the digital pad has a load of only 10fF, so my frequency divider was designed to drive a small load.
So the analog IO pads in the PDK...
Hi,
I am designing a Flash ADC that operates at 1Ghz in umc 65nm. The output of my ADC goes to a frequency divider to divide the frequency to 250Mhz. However, the propagation delay of the PADs is around 3 to 4 ns. I am afraid that the output bits of the ADC through the PADS will get corrupted...
Thank you for the mail. I will try to do that.
Maybe a cause of this might be because the digital encoder is designed using the standard cells which has the substrate tied to global VSS and VDD. When I integrate the analog section with the digital section, the different biasing of the analog...
I am designing an ADC in umc 65nm which operates at 1GHz. The analog section consists of the sample and hold and a bunch of comparators. The digital section consists of an Encoder(synthesized in Cadence Encounter).
When I connect the analog section and digital section to different power...
The error I am getting is
*Error* Could not Evaluate property ad of value ((iPar("sb")) * iPar("w") / iPar("fingers")) + (iPar("sd") * iPar("w") / iPar("fingers") * 0) for the instance: I0_MNM165.
The single level transmission gate calibre is working alright. But when i create a chain of them...
I am designing a chain of transmission gates in 65nm but having a problem with the calibre view generation. For a single transmission gate, the DRC, LVS and PEX works perfectly and I am able to extract the calibre view. Now, when I make the top level block consisting of a bunch of transmission...
I am designing a 4 bit ADC sampled at 1Ghz. When I apply an input sine wave of 500Mhz, and do SNDR calculation, I get a very low SNDR(~10 db) giving an ENOB of less than 2.
I have seen in many ADC papers where they apply an input which is at the nyquist frequency, yet still achieve a high SNDR...
Hello,
I am designing an ADC using Cadence design tool. When i extract the data from cadence to run FFT analysis on matlab, I found out that the time steps from the cadence data are not uniform. Due to this the FFT analysis shows a very low SNR.
Is there any way to extract the data from...
Hello,
I am working on a project to design a 4-bit Flash ADC for a digital transceiver.The flash ADC should meet the following specifications:
Input frequency: 100MHz-500MHz
Sampling Rate: 2GS/s
VDD= 1.1V
signal voltage range = 0.5V peak-peak
I am using cadence with umc 65 technology.
I am...
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