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Recent content by sp_harikrish

  1. S

    choice of Prepeg. Any rules ?

    i think, he was asking about the solder Masking details.
  2. S

    requirement of loop filter design in DPLL

    Hi, I have an requirement of DPLL. The requirement is like this. I have an phase detector in VHDL and the difference output is given to processor to do the rest of things like loop filter and voltage input to VCO( which is voltage controlled oscillator) present in the board. can any of come...
  3. S

    just to make shure: blind vias in altium

    Hi, see basically whatever your blind vias will be reflected in your drill files. You may not need to specify. Only thing you will have to make sure that your manufacturer will be able to supprot for such kind of vias. -Sp_Harikrish
  4. S

    Which VHDL/Verilog Editor is the best ?

    verilog edit tool i think modelsim and xilinx are the best. You can even get a student pack(i think).
  5. S

    Who are the largest VLSI circuit designers?

    Hey, i have an question. who are the giant VLSI circuit design
  6. S

    What's the main difference between FPGA &CPLD ???

    They are basically differs in architecture. Logic cells and their size are vary. CPLD has very low speed where as the FPGA has MUX and high speed design. CPLD has ROM based and FPGA has RAM based. FPGA has more logic cells
  7. S

    the PCB masks and layers

    Top mount is - top layer Bottom mount - bottom layer Silkscreen is - Component outline Pad is general term and padstack is pad in which all the layer it exist.
  8. S

    analog and digital ground

    Ferrite bead will add inductance. For the potential between them is there is no problem But it act as a filter in the high frequency signal. Hence it will prevent ripple due to anlog circuit noise.
  9. S

    Why we choose routing angle of 45 degrees?

    Re: routing =45' Hi, one is to avoid the cornering problem.The other one is the capacitance effect in 90 degree angle pcb trace will have more rather than 45 degree.
  10. S

    Orcad Schematic/layout libraries

    Hi, If you have the datasheet for each, you can easily create for it.
  11. S

    What is the Best way to route signals on split plane.

    split power planes HI, If your signal crossing only the split power plane, then there won't be problem. Since you have the gorund above the split plane. That is the signal will take the immmediate return path below which the signal is routed. In your case the immediate ground path is ground...
  12. S

    Joining ANGD & DGND in one place???

    The ferrite will basically act as a filter. Which is basically eliminate the high frequency noise due analog circuits enters into the digital section. If you shrot with the normal 0E resistor, you will not have any filtering circuit. The noise due to the analog circuit will get coupled into the...
  13. S

    Issues and questions about PCB routing

    PCB routing No problem, But you make sure that the high frquency traces are routed through an guard traces and prefect impedance termination. You can even achieve in two layer board.
  14. S

    PCB Material Dielectric

    All the dielectric material vary for frequency and temperature.
  15. S

    Help me with writing a VHDL code

    Re: help in vhdl Hi, it looks like a shifted signal on each rising edge of the clock. you can use shift register in this case.

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