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The technology refers to the minimum allowed gate length. So in your circuit there may be 360nm as gate length but there cannot be lengths less than 180nm.
Critical signals which are active on rising edge of reference are shielded with VDD
If the signal is active on the falling edge of reference then GND shield is used
It depends on the block for which you are doing.
If the substrate is very noisy and you want to protect you Ground from the substrate induced noise then the best way is to have a separate pin for the subatrate at the block level and finally connect them to the gnd pin at the chip level. This...
Calibre VS Hercules
Please tell me
1.The advantages and disadvantages of using Hercules tool compared to calibre tool for Layout Verification.
2.which tool is Layout designer friendly, Virtuoso or Synopsys LE?
Hi Paramjyothi
Thanks for the valuable suggestion.I am working on 65nm tech.
I have placed the trans in such a way that they are arranged in a source/drain source/drain pattern so that the direction of current flow will be uniform.
It will be of great help if you could tell me which is...
I am trying to match the diff pair using common centroid.
Please go through the attached layout.
1.give suggestions to,improve this layout.
2.correct this layout If my approach is wrong with respect to matching or routing parasitics
Regards
SP24
Re: Poly layer Route
even i had the same issue when working with TSMC foundary. but currently i am doing it for renesas 65nm tech ,here i am not getting this DRC violation.
I have the following queries as i am doing an LDO Layout.
1.Do i need to shield th inputs of error amplifier?
2.what constraints to be followed to reduce the IR drop of the Output.
3.Is there any other major care to be taken while doing an LDO layout?
4.what will be the critical issue in LDO...
But if i place the transistors as (source)-A-(Drain) (Drain)-B-(source) the current will flow in the opposite direction.So i felt arranging them as Source drain source drain is better.correct me if i am wrong
sdsdsdsdsdsdsdsdsdsd sdsdsdsdsdsdsdsdsdsd
I am trying to match an N-mos diff pair(10 fingers each) in the following pattern,
A B A B A B A B A B
s d s d s d s d s d s d s d s d s d s d
B A B...
Re: Poly layer Route
I am not getting any DRC violation for poly enclosure by NI or PI.
In that case do u suggest me to leave poly as it is without NI or PI enclosure?
I am using poly layer to connect two gates.The distance between the two gates is 2 um and i am using it in a NAND layout. I am working on 65nm process.
1.Is it necessary to cover the poly routing connecting the two gates with N-implant or P-implant layer?bocz i have routed just like metal in...
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