Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
multiplication waveforms circuit
Can any body help to provide the circuit that can perform
the waveform as shown in the figure above.
It is the clock multiplication!:D[/img]
I am a degree student and i have a project regarding with the using of High
Level Data Link Control (HDLC) in frame relay.
But i surf out of the internet to find the related information but nothing get, so
can any legends plz tell me what is HDLC in frame relay and provide me
any related info...
critical warning: register will power up low
Im using quartus II 6.0 to simulate my circiut, but there is an
critical warning comes out and said that :
-----------------------------------------------------------
Critical Warning: Ignored Power-Up Level option on the following nodes --...
pic16f877a hyperterminal
I recently try to send data to and from PIC16F877A via uart and the result show
in the hyperterminal, but there is the problem that nothing comes out
at the hyperterminal.
here is my source code,
--------------------------------------------
LIST P=16F877A
#INCLUDE...
pic16f877 spi
I am new to PIC and ask that does anyone knows the steps of SPI configuration
for PIC16F877A.
If possible gives some source code examples!
Thanks!!!:D
Thanx, but i have to run full compilation first right, bcuz smart compilation is
a recompilation option, it skips any unchangeable module during compilation.
If i dun want to upgrade RAM of my computer,
Is there another ways to increase the speed of compilation?
when using quartus tools to compile the correction of my Dual port RAM design,
it takes me hours to compile and synthesize the source code file.
The RAM with only the size of 64 bytes, successful compile after 5 minutes.
The times increase linearly when the size of the RAM double,
let's say...
im trying to run a package i'd created using quartus tools but when i run the compilation, an error with the following appear in the message box.
the following is the package header of simple full adder (fulladd_package.vhd):
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE...
how will you create a user defined package
im trying to run a package i'd created using quartus tools but when i run the compilation, an error with the following appear in the message box.
the following is the package header of simple full adder (fulladd_package.vhd):
LIBRARY ieee ;
USE...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
