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when I use "Verify --> Verify Process Antenna" to verify ant violation in Encounter,
there are 2 resuts ,one is named "Area Ratio" the other is named "Side Area Ratio",
Can you tell me what's the difference between those.
Fix setup violation you can insert buffer,optimize fanout,upsize instance
If you fix the setup you must large the require time,so it must inpact the holdtime!
I want to check the design which nets have been set the dont touch attribure in encounter, Does anyone tell me the command for it.
Astro has the command by write_design to dump the file that contains the don't touch/don't use information.
Thank you!
Bellow is the assura lvs problem ,Is the option missed in the setting file.
Does someone can help me to solve it.
Thank you!
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****** rpposab_ckt(Generic) <vs> rpposab_ckt(Generic)...
There are many pins in the Hard macro,and per pin connects per buffer,
I want to place the buffer near the connected Hard macro's pin,
In Astro ,I knew the command "astMagnetPlace" can do it!
But What can I do for it without setting region in Soc Encounter tools.
I knew QRC can extract the RC from LEF/DEF,
but if I want to extract the RC from gds,Can you tell the flow for it.
Is it the same as Assura RC extract flow
##must run the lvs ,and then RC extarct by rsf file ?
Thanks!
Do you have Encouter or Astro's technology file,
if you have it ,you can use Encounter /Astro to read the lef/def,
then export the gds only have the metal /via/pin text.
Re: Max Tran & Cap
There are quite diffierent from setup/hold check,
Transition is the time delay form 0 to 1 or from 1 to 0,
and the capacitance is the cap of the cell's output,
so the Transiton and the capacitance must be defined in the library(.lib),
the timing delay will be large when the...
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