Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Sorry for the late reply,
Assigning a unique net name for all the traces ultimately getting together is of course a logical way.
If I connect two net names to each other, altium selects one of them as a common net name. The question is: How can I select it? Not Altium. In hierarchical designs...
Hi all,
In a big schematic design, there are several net labels connected to the same node.
When I upload sch to pcb, one is selected arbitrarily. Therefore I may see 'ENABLE_XXYY' label on traces/vias/pads etc. instead of 'GND' for my global gnd.
How can I select the one I want?
Thank you.
Hi GUMY,
I think your suggestion is very good but holes of the vias do not seem to be filled. They may get rid of them at the end of the process. Thanks.
Thanks Mattylad,
It is logical to strengthen a via which will be used as a test point. As far as I know, via plating method is also used for thermal purposes.
Actually the term, 'vacuum-tightness' had confused me. Thanks.
Hi,
I encountered a blue mask applied to some specific vias of a PCB.
When I search for it, I found the following example:
Do you know the aim?
"vacuum-tightness for the in-circuit test" is their explanation but I could not understand what the aim clearly is.
Here is the link: **broken...
Hi,
Brooks' and Johnson's articles are very helpful:
**broken link removed**
http://www.ultracad.com/article_outline.htm
You can go 'links' section of Novak's web page for a list of further tools, articles, books etc. His list is perfect:
http://www.electrical-integrity.com/
Hi,
I have exactly the same problem for not an opamp but a voltage translator but the logic should be the same.
There is no freq. vs gain curve, no rise time. What I only have is the propogation delay and I need BW.
@varunkant2k,
I agree as f3-db≈1/6RC.
However, I do not agree with the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
