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Did take a look. Was a little confused. Here is the sequence I was thinking about.
stage 0 - 2xclk
stage 1 - 1xclk
stage 2 - 1xclk
stage0 has 1 2x flop launching data bits every clock cycle
stage 1 has 2 1x flops. 1 clocking posedge and 1 clocking negedge.
So if you assume 4ns 1X clock...
setup and hold violations can happen on the same path at different corners if the variations on the path are big. If the path is well optimized for loads and transitions, then the probability of setup and hold on the same path should be pretty tough. Do remember the setup takes the worst delay...
Hmm.. Only neg-edge huh.. How about this. The flop has a clock-gating cell in front of it. When A is HIGH, clock-gate always active. When A is LOW, clock-gate ENABLE delayed by 2 clock-cycles.
Do you think this will work?
1 2X flop goes to 2 1X clocks. One 1X clock on rising and one 1X clock on falling. So you king of assume first 2X clock data is captured by pos-edge 1X and 2nd 2X clock data is captured by neg-edge 1X.
I'm not a big fan of this method. But here is an option.
Dump out a verilog. Change all hvt_ to svt_ and read the netlist back into to ICC/whichever. That tool should be able to generate the ECO script for you.
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