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Recent content by solvall

  1. S

    LDV51 with RHEL 5.2 x86_64

    When I start license daemon, it fails to run LDV51 and get the following message, relocation error, symbol errno, version GLIBC_2.0 not defined in file libc.so.6 with link time.... does anyone has such experience? how to solve this problem ?
  2. S

    I need sample design or textbook to learn SOC

    I don't think this is one I need. would you double checkt your attachment?
  3. S

    MPEG4/H264 + Audio codec

    is there any standard to define stream format for Video+Audio? Video coding in MPEG4/H264 Audio coding in MPEG4/MPEG2/MPEG1 or WMA9 can you recommend some IPs that can process A+V stream? any standard spec. for stream format . such as MPEG2 transport stream format? any transport stream...
  4. S

    I need sample design or textbook to learn SOC

    I have no idea how to learn SOC design. I want to know how to boot OS. where to store your OS, hardware driver. any detailed textbook has such exapmle to show overall SOC design from verilog code to Software programming?
  5. S

    Can you contract to DVB-T/ATSC Demodulator?

    Do you have any ready algorithm or c-model that can be applied to ASIC ? I need Verlig RTL codes to build DVB-T or ATSC demodulator. 1. ADC for demodulator 10-bit precison. 2. DVB-T demodulation algorithm: C-model or Matlab source codes. 3. ATSC demodulator algorithm: C-model or Matlab source...
  6. S

    Can you contract Audio Cdec IP?

    I need some audio IPs for my project. codec IPs : WMA9 MP3 MPEG2/MPEG4 Audio formats Hardwired RTL or DSP software based is ok. RTL Codes shoulde include verilog RTL codes, C model source codes. DSP software based: ADSP2181 , TI32050, ARM9, or MIPS324KE
  7. S

    Avoid bit-blast I/O ports on Synopsys synthesis

    bit blasting I did have verilogout_single_bit set as false. but the problem is still the same as follows, module ABC ( .PTA({PTA3, PTA2,PTA1,PTA0}),... ) input PTA3, PTA2, PTA1, PTA0; endmodule ------------------------------------- I want to retain PTA as bused ports...
  8. S

    Avoid bit-blast I/O ports on Synopsys synthesis

    bit blast I have a module as shown below, in RTL module ABC ( PTA, PTB); input [3:0] PTA; output PTB; ... endmodule after synthesis, netlist in Gate-level obtained from Synopsys Design Compiler module ABC ( .PTA({PTA_3, PTA_2,PTA_1,PTA_0}) , PTB); input PTA_3,PTA2,PTA_1,PTA_0; output PTB...
  9. S

    Buying MPEG2 IP core in HDL source code

    I would like to buy your MPEG2 IP core in HDL source code. Do you have this IP available now?
  10. S

    Source code for Microblaze RISC CPU

    Do you have any experience with Microblaze RISC CPU? some Xilinx FPGAs have built-in Microblaze RISC CPU. but we can't see its hdl source code. where can i find its source code.( synthesizable rtl)
  11. S

    disable REHL 4.0 Removable storage

    I would like to disable USB flash disk and CD/DVD writer . is there any setting to disable flash disk ,CD-DVD writing? i would like to keep data secure .
  12. S

    Looking for 8051 HDL code compliant with intel 8051

    need your experience I ''m trying to use FPGA to run real-time 8051. But my HDL code is not fully compliant with Intel 8501. do you have 8051 HDL code that is fully compliant with intel 8051
  13. S

    Where to find HDL processor in synthesizable Verilog/VHDL?

    HDL experience Where can I get this microprocessor in synthesizable Verilog or VHDL code?
  14. S

    SD/MMC development board and r/w source codes in C

    could you recommend that any development kit for starters? the kit better include firware source codes in c and uC + system schematic
  15. S

    Can you implement a line locked PLL with jitter ?

    Re: PLL Jitter yes, it's possible. but jitter may also depend on line-up pulse

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