Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by solidstate

  1. solidstate

    Output resistance of current mirror - Simulation Setup

    No worries, glad we cleared it up. One other thing you could look at is increasing the target Vds and/or the L of the bottom devices. Right now, the Rout of your cascode is higher than that of the current source itself -- I think that's quite unusual.
  2. solidstate

    Output resistance of current mirror - Simulation Setup

    Oh boy... I hope you're not trolling? The gain of the amplifier improves the output impedance... search for regulated cascode or gain-boosting... Here I was expecting to see some basic cascode bias stack...
  3. solidstate

    Output resistance of current mirror - Simulation Setup

    At this point, I also don't understand. Can you annotate gds? It is worth checking that gds = 1/rout Also, can you post the full schematic of Current_Source?
  4. solidstate

    Output resistance of current mirror - Simulation Setup

    Thanks! The small signal calculation looks reasonable. Not sure what is going on. Could you try to remove L0, C0 and V0 (the current source), apply an AC stimulus to V1 and re-run the sweep? Then, take 1/i(v1) as your output impedance and compare?
  5. solidstate

    Output resistance of current mirror - Simulation Setup

    M0 is in triode, I suppose that should be fixed first. Then, are you sure you can use ±1.2V bipolar supplies here? It looks to me like those are 1.2V devices. M1 Vdb might be way too high at the moment?
  6. solidstate

    [SOLVED] frequency compensation of 2 stage opamp

    You are running much less current in your output stage than in your input stage. Replace your voltage biasing with current mirror / replica circuitry throughout, starting with M9 and M11. Before you do any further simulation, do some calculation on what the gm of the first stage and the gm of...
  7. solidstate

    gm/Id value of pmos is more than 35

    I think the PDK is fine. You're just looking at extremely low Vgs values and extremely low currents. You are using minimum length and perhaps the model includes some Vds-dependent Ids current source, which would appear as increased gm/Id, indeed. One thing you could do is to run a transient sim...
  8. solidstate

    How to make a low ON resistance with NMOS with reasonable length and width

    Also, maximize VGS and maximize VBS within the reliability limits of the process.
  9. solidstate

    common gate comparator offset

    You can apply a voltage ramp to Va-Vb and record at which voltage the output toggles. You could consider adding a second stage. That allows you to keep the MP1 and MP2 drain voltages equal throughout, which will help with (systematic) offset and hysteresis.
  10. solidstate

    Resistive CMFB circuit question - capacitors

    I'm aware of only your first suggestion, especially if it's a continous time circuit. Two resistors across the output will require a current if the differential output is nonzero, and, in an OTA, they will lower the voltage gain; therefore, they're typically taken as large as possible. The...
  11. solidstate

    can someone recommend a good bi-cmos book?

    I am also interested in this..
  12. solidstate

    What is the function of the attached circuit?

    Working of circuit Looks like an LDO with some bypass feature?
  13. solidstate

    Detect human from a sensor on the ceiling

    I would suggest the use of an image sensor.
  14. solidstate

    mixed-signal PCB design questions

    This comes highly recommended: http://www.hottconsultants.com/pdf_files/june2001pcd_mixedsignal.pdf

Part and Inventory Search

Back
Top