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I got a similar window, did you try to double-click on the entries?
Btw, you have a Calibre menu in Virtuoso and run it interactively with Virtuoso, right?
Hi there
I haven't run into this, after extraction when I open RVE I can see the RC associated to each node being reported and I can click on them to see there location of the element in the layout. Perhaps you can attached a screenshot of what you are seeing?
Hi there,
you might want to define the Power and Ground nets in calibre settings, so that it knows what nes are they. Sometimes ERC errors provide useful information, sometimes they are just due to Calibre being confused...
Hi erikl
Thanks for the reply. The nmos_rf cell is a pdk component, it doesn't have a schematic view. I think right now the extraction tool has to stop at symbol. One thing I can think of doing is to declare the cell as a black box in Assura, but then I'll have the risk of messing up the...
Hi all
I'm a student new to circuits. Recently I've been working on a CMOS tapeout using TSMC 65nm RF CMOS process and ran into an issue with the foundry RF MOSFETs. After spending some time debugging I'm still puzzled. I'd really appreciate your input. I currently left some of the numbers in...
Hi All
I'm a graduate student new to circuits. Recently I've been working on a CMOS tapeout using TSMC 65nm RF CMOS process and ran into an issue with the foundry RF MOSFETs. After spending some time debugging I'm still puzzled. I'd really appreciate your input. I currently left some of the...
It means they intersect. And HFSS had a hard time determining who should overwrite whom. I had this too, this happened when both objects are conductor with finite conductivity. If you have metal intersecting dielectric, it's usually OK, the metal will take the priority.
Hi all
Glad to join the group, just a general question as how you usually choose between DrivenModel and DrivenTerminal with Lumped Port and Wave Port. I actually don't quite understand the physics behind these four terms, would really appreciate your comments.
Another more specific...
Would you mind posting the Z11 vs. frequency trace? And, how do you connect the lines to your DUT? What's the dimension of the DUT compared to the PCB trace? You calibrated out the electrical length for both methods respectively, right?
Hi
Anyone knows how to export s-parameters from HFSS in batch mode? I swept a few design parameters and got a pile of s-parameters for different designs that I can use for circuit simulation, I feel exporting manually so many files is quite error-prone.
thanks,
Ran
Thanks for the explanation.
I was doing a one-port simulation the other port of the inductor is simply short by a PEC boundary condition. I don't quite understand in this case why Y and Z-parameter give slightly different result.
I think one problem is how you define Zeven1 Zeven2 Zodd1 and Zodd2.
Assume the situation is that you have two signal lines S1 and S2 and one shared large ground line G. In the symmetric case, S1 and S2 has exactly the same dimensions, so you place PEW or PMW in the middle that does not alter...
If you model it as a 2-port element, make sure you have a good return path (the two port need to share ground).
To talface65, I somehow found using Z-parameter generates more accurate result than Y-parameters.
Hi erikl
I think the expression MOAT makes sense because this layer blocks BF2 doping and makes a resistive guardring around the circuit part you want to isolate, just a like a moat.
regards,
Ran
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