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Recent content by smilermd

  1. S

    Help regarding Level shifter IC

    You can use a voltage clump device. From TI **broken link removed**
  2. S

    IC-Prog 1.05C Problem

    ic-prog privileged instruction ICprog don't have acces to COM port, you need to do something like this **broken link removed**
  3. S

    Why I can't get the correct counter?

    topics counter always at 0 Ahh, ok. Then remove "or en" i have put this to make simulation faster.
  4. S

    Why I can't get the correct counter?

    mixed single and double edge expressions are not Why not? It runs, and it does what you need.
  5. S

    Why I can't get the correct counter?

    verilog mixed single and double-edge expressions Try this: module edgectrl(clk, clr, en, outnum); input clk, clr, en; output[7:0] outnum; reg[7:0] outnum; always @ (posedge clk or negedge clr or en) begin if(clr == 1'b0) outnum = 0; else if(en == 1'b1) outnum = outnum +...
  6. S

    If anybody need help in EAGLE, ask me in this POST !

    pcb eagle thermals Hello. Can anyone tell me how to add 2 pins to a symbol with the same name. For example i have a chip with many GND pins, and i want them to have the same name in the symbol. Thanks
  7. S

    What should I learn to become a chip designer?

    Re: vlsi beginner First of all you should decide what types of chips you want to do: analogic, digital or mixed designing. For digital desing you can start looking to VHDL, Verilog languages. First of all you can try you powers in working with FPGAs, CPLDs. This will help you to understand very...
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    Help in minimizing macrocells in a Altera, in VHDL

    Help in minimizing macrocells in a @ltera, in VHDL You're welcome. I don't know why integers are better than STD_LOGIC_VECTOR, may be this depends on vhdl synthetiser or on device.
  9. S

    Help in minimizing macrocells in a Altera, in VHDL

    Try the next clock divider, it should help. divide_clock: process (clock,Start) begin if Start = '0' then contador <= (others => '0'); else if (clock 'event and clock = '1') then contador <= contador + 1; end if; end process; clk_out <= contador(2);
  10. S

    problem in implementing state machine in vhdl

    I think that the code for clk_st is shifting once, you receive 2 times shifting because in the next cycle, in the state compute, you are shifting one more time. You can't do this in one state, the shift and xor operation happens at the same time.

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