Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
pcb eagle thermals
Hello.
Can anyone tell me how to add 2 pins to a symbol with the same name. For example i have a chip with many GND pins, and i want them to have the same name in the symbol.
Thanks
Re: vlsi beginner
First of all you should decide what types of chips you want to do: analogic, digital or mixed designing.
For digital desing you can start looking to VHDL, Verilog languages.
First of all you can try you powers in working with FPGAs, CPLDs. This will help you to understand very...
Help in minimizing macrocells in a @ltera, in VHDL
You're welcome.
I don't know why integers are better than STD_LOGIC_VECTOR, may be this depends on vhdl synthetiser or on device.
Try the next clock divider, it should help.
divide_clock: process (clock,Start)
begin
if Start = '0' then
contador <= (others => '0');
else if (clock 'event and clock = '1') then
contador <= contador + 1;
end if;
end process;
clk_out <= contador(2);
I think that the code for clk_st is shifting once, you receive 2 times shifting because in the next cycle, in the state compute, you are shifting one more time.
You can't do this in one state, the shift and xor operation happens at the same time.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.