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Recent content by skn.1357

  1. S

    Small doubt regarding verilog

    Hi sina.parsnejad, what do you mean by "low power elements"? I think it's the high Vt transistors, isn't it?
  2. S

    Several doubts regarding Slave chain in RTL

    Hi, I have several doubts regarding slave chain and it's operation, please clarify: 1. why to use slave chain, we can use just some register bank? I read that chaining is time efficient, how? 2. there are several types of interfaces to connect these slaves, such as AHB, I2C.. how decide which...
  3. S

    Small doubt regarding verilog

    Hi, For ensuring low power consumption you should follow these design rules: 1. use high threshold device (Hi-VT) so that leakage can be minimized, 2. by modifying the logic structure such that the toggling rate of transistors can be minimized, 3. use gated clocks, so that idle portions of your...
  4. S

    gatelevel simulation necessity after LEC

    Can anyone please let me know why all feedback loops are broken before doing equivalence check? Is flattening the netlist does this work, if not then why we flatten design before LEC, I read it makes scan chain and CTS logics identifiable to tool for mapping???? Thanks in advance.
  5. S

    what is difference between layout exchange formate and library exchange format?

    Hello there what is difference between layout exchange formate and library exchange format? are they both represent the same thing or are different?? thanks in advance...

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