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Thanks a lot, but I can only get FRAM view from the foundry, no CEL view available, I'm sure about that,
so how can I DRC without CEL view?
---------- Post added at 06:44 ---------- Previous post was at 06:41 ----------
I don't have any other gds libraries...
Hi,
I've designed a digital chip with Astro, and there's no CEL view in the Milkyway Lib,
when I check DRC with calibre, it will cause many error because there no standard cell view in the gds file,
so, how can I check DRC with calibre now?
thanks!!!
Hi, all
my foundry library power unit is different between standard cell lib (pw) and I/O lib (uw),
whenI open a design with IC Compiler, it will give a warning and an error like this:
what can I do with such difference?
thanks!
Hi,all
I know we need pad fillers to continue the power ring between pads,
but I think there're some metal rails in those pads already, so shall we need one more step such as create_pad_rings to complete those power rings?
thanks!!
hi,
I'm not familiar with ICC, I used Astro before..
now I don't know why everytime I use derive_pg_connection to conncet P/G, ICC will prompt this:
anyone knows why?thanks!!!
thanks again,
but for this step: 4.Add the layers which Astro discarded before.
so you mean the GDSII file dumped by Astro doesn't contain those layer? then you need to add them in candence tools? but how?
or you mean the GDSII file contain those layers, but cadence won't display them by...
Hi,all
I have a analog macro gds2 file from IC5141, and I need to import it into my Astro to finish the final layout, but I find there are some layers such as LW, XW, that I don't have in my Astro .tf file.
so, after I StreamIn the macro gds2 file into Astro, these layers disappear, I can't see...
Hi,all
I have a gds file which don't contain any CEL view, because the foundry won't provide those, so I only got Route view in gds file, still I want to do DRC with calibre, but, calibre will prompt many errors like this:
so, anyone can tell me how to bypass those Cell check and only do some...
Hi,all
what's the difference between wirebond and C4 when we mentioned as IO type?
I think it's on the top of the top-most metal in IC design, but I don't know what's the difference and how to use it.
thanks!
Hi,all
Is there any have the experience of mixed-signal IC design?
I have a problem about the synchroniztion between digital part and analog macro.
we know, after CTS, there will be a delay between CLOCK source and DFFs' clk, and it's done automatically by APR tool such as Astro, but in the...
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