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Recent content by shivapugal

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    timing analysis for DDR2 designs?

    Hi, Rank is based on the no of chipsets and DIMM module you are using. DIMM module can contain upto 4 ranks means 4 chipset signals.If you have 2 rank you need to select 2 i believe. I do not use hyperlynx for timing analysis. sorry i could not support more on this. Shiva
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    timing analysis for DDR2 designs?

    Hi We cant do timing analysis in hyperlynx unless we get ddrx analyzer which is a separate package in hyperlynx. contact your filed representative to get the license. we need to take the setup and hold time from datasheet. Thanks Sivalingam
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    DDR2 Signal Integrity Simulation & Timing Budget calcula

    Hi Amarnath, Well you have cleared the overshoot problem by adding VTT termination at the last memory.. I hope the 10pf capacitor will clear the non-monotonicity and causes the signal to rise/fall smoothly, but it do increases the rise/fall time anyhow i think freescale also suggest to...
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    S-parametrs definition

    Hi, Scattering-parameters are used in high speed signal analysis to find out the reflection(S11) and insertion(S12 OR S21) losses. It depends on the no of ports we are using. lets take an example that we have 2-port network 1- input 2-output. In s-parameter Sxy x = output y = input. if S21...
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    timing analysis for DDR2 designs?

    Hi, I have done lots of timing analysis on DDR2 memories. Post your queries here. Shiva
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    DDR2 Signal Integrity Simulation & Timing Budget calcula

    Hi, If it is DDR667Mbps, then you must simulate with the following, data/data mask nets as 667Mhz, strobe(dqs), clock = 333Mhz control nets = 333Mhz address/commnad = 333Mhz if it is IT clocking scheme or 166 for 2T. For the simulation you must use models from the micron for the memory...
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    DDR2 Signal Integrity Simulation & Timing Budget calcula

    Hi, We cannot run a cross talk analysis in LINESIM. we need to run. There is only one way to get the crosstalk analysis report in hyperlynx is by running the batch simulation report. It just provides only one report for relection, crosstalk all. Regards Shiva. ---------- Post added at 09:24...
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    Hspice training in india

    Hi All, Does anybody knows good institute to learn HSPICE basics and advanced courses related to circuit and signal integrity analysis? Kindly provide the details and share your experience if anybody undergone any training. Thanks Sivalingam
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    DDR2 Signal Integrity Simulation & Timing Budget calcula

    Hi, DDR667Mbps is a data rate. U have to simulate DDR signals in the below frequency. 1) Data - 667Mhz 2) CLk - 333.5Mhz For the address lines u need to check whether 1T or 2T clocking scheme is adapted. If 1T clocking scheme is used you need to simulate the Address/Command/Control signals...
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    DDR2 Signal Integrity Simulation & Timing Budget calcula

    Re: DDR2 Signal Integrity Simulation & Timing Budget cal Dear All, There is no need of any termination on the board for the data/mask/strobe signals in ddr2. We have 3 alternate ODT values in the memory chip i.e 50/75/150 ohm which can be controlled using ODT pin from processor. Similarly in...
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    How to connect mac and physical chip on same board?

    mac and phy chip HI all, If we have an mac chip and an physical chip in the same board how the connection between them will be achieved? will we need to use rj45 connector? kindly guide and suggest whether it can be done or not. Thanks Shiva.
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    Difference btw Back end and Front end in VLSI

    difference between frontend and backend Hi arjun, Thank u for your quick response. two more question will the back end designed according to the rtl coding? after the coding will we fuse the code into the chip or just the back end is designed according to the rtl coding same like schematic...
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    Difference btw Back end and Front end in VLSI

    what is meant front end in vlsi Hi all, Im an vlsi student I searched in the net but i couldn't get the exact difference between Back end and Front end methodology in VlSI and ASIC design flow. i feel it was much differ from pcb layout back and front end design. can anyone clear me this...
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