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Recent content by shivakumar043

  1. S

    Is shift register is sequential or combination?

    I have a confusion, is shift register is sequential or combination.....
  2. S

    Why we use latch between two clock domains?

    Re: Latch Hi, I think for mixing clock domain or to solve skew problem latches are used, when you are mixing two clock domins you may get skew , because of skew you may lose the data, in that case these latches hold data and avoids lose of data.
  3. S

    Glitches in AND gate with two inputs

    Re: glitch Hi, if your circuit is synchronous you need not warry
  4. S

    Why PMOS for pull up and NMOS for pull down?

    Hi, PMOS transfer good value of 1 and NMOS transfer good value 0 (means you can get rail to rail swing)
  5. S

    What's the purpose of DFT (design for test)?

    Re: DFT :design for test Testing is requried to prevent bad product reaching the customer. when you add testing logic to your design it comes more testble(i.e controllability and observablity of the design). so that probability of bad product reaching the customer decreses.
  6. S

    what advantages does DC XG mode have over the old version.

    Re: what advantages does DC XG mode have over the old versio Hi, Dc runs faster in XG mode and consume less memory(for writing output files). I have a document attached with it that may be useful to you. Regards shivakumar
  7. S

    The difference between RTL code and HDL code

    Re: diff b/w RTL and HDL HDL is harwarre description language . One can write RTL using HDL
  8. S

    Does the architecture of the design change after synthesis?

    Re: Synthesis synthesis basically optimization+translation+mapping(to technology lib). After synthesis u can get the netlist in .v or .vhd . you can check this netlist by running your test bench. I think u can also perform formal verificaton that is RTL vs netlist.
  9. S

    Help with interview question #1

    1.Hybrid adder: Carry select adder, carry skip adder
  10. S

    How to calculate the standard cell height?

    standard cell track hi, Usually , horizantal routing track width depends on (M2 min width) vertical routing track width depends on (M3 min width) assuming VHV routing architecture.. Normally M2 & M3 will have same min. and max. dimensions amara i am basically into DFT i u want...
  11. S

    Does "scan_enable" need double space ?

    can you explain what double space means..
  12. S

    How to calculate the standard cell height?

    routing track standard cell Hi, Normally Cell height = integer multiple of (horizntal/vertical)routing pitch or track. for power & ground = need 4 tracks for I/O pins = need 4-5 tracks for routing = need 2-3 tracks. So a standard cell can be available in 9-12 tracks...
  13. S

    Regarding Boundary scan

    Hi all, I am trying to insert Boundary scan to my design first time (using BSDArchitect). After inserting the Boundary scan i got 4 file (.bsd, .v, _tb.v, top.v). problem is it has inserted pullup to the TMS, TRST, TDI and this is causing problem in synthesizing(i am using DC for synthesis) pull...
  14. S

    Looking for tutorials to learn using DC2000.05

    Re: [Help] How to learn DC? Hi, Best way to learn DC is through by studying DC manuals, before that get an account in the solvenet its very usefull. you will get answer to your most of the questions, i think you can also get so many usefull materials.

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