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Recent content by shilong_xu

  1. S

    Help..........Design with multi-RAM under SMIC 130nm process

    Re: Help..........Design with multi-RAM under SMIC 130nm pro thanks papertiger! but at present, our algorithms decide the whole RAM blocks, how to build 5-10 blocks? how to layout to this type of ciuciut? any guidance?
  2. S

    what is the difference between digital, analog, RF IC proces

    Re: what is the difference between digital, analog, RF IC pr thanks, in general, i know the analog an RF models include the spice parameter, but what included in the digital models? they are not the spice models?what is the mask difference between digtial analog and RF in detail?
  3. S

    what is the difference between digital, analog, RF IC proces

    hi, everyone, at present , i am a littel confused about the IC process, what is the difference between digital, analog, RF IC proces? Any additional mask? or only the simulation models? thanks
  4. S

    How to set up the DC field of MOS in RFIC?

    hellow, everyone How to set up the DC field(liner and saturation) of MOS device during RFIC design? such as in LNA， PLL， PA，whether have some principles to follow? thanks!
  5. S

    TSMC 0.18 RF designkit for ADS2005A

    you can use designkit setup, and set the right path, everything is ok. good luck!
  6. S

    help me about ADS2005A installation!!

    hi,everyone could someone give me some advice about ADS2005A installation problem? it always appear that "the system time have been setback", why? and how to solve this problem??
  7. S

    CMOS RFIC layout considerations

    hi, all someone can give me some system guideline(books or article) about CMOS RFIC layout considerations? thanks
  8. S

    Do I have to consider the transmission line effect in 0.35 RF CMOS LNA design?

    Re: question about RFIC thanks! in general, but the critical size is 1/10 of wavelength or 1/20 in practice?
  9. S

    Do I have to consider the transmission line effect in 0.35 RF CMOS LNA design?

    I want to design a 0.35um RF CMOS LNA, whether I must consider the transmission line effect? thanks
  10. S

    how to isolate the LO leakage in zero-if receiver?

    thanks khouly but how to solve this problom in RF CMOS process? and whether considering the transimission line effect in CMOS RFIC design? my rf is in 1.1-1.6GHz thanks
  11. S

    how to isolate the LO leakage in zero-if receiver?

    hi, everyone how to isolate the LO leakage in zero-if receiver? such as in schemetic or layout? thanks a lot!
  12. S

    microprocessor core verification

    hi, everyone at present, i have a project about microprocessor IP core, but how to verification, especially its fuctions, if some common principles? thanks
  13. S

    RF PCB designing guide

    could someone offer the detail books about the RFPCB design? i have the project to do, but i am a beginer, how to start for me? thanks
  14. S

    TSMC 0.18 RF designkit for ADS2005A

    I want to do the RF to Zero IF, but i have not the original schemetic for single compenent, such as LNA, mixer, PLL, et.al
  15. S

    Help me start a zero-if GPS receiver RFIC project

    Re: about receiver RFIC at present, I have the specifications, but i have not the specific component schmetic, such as LNA , mixer LPF et.al in addition , I have the corresponding process lib too how do i start?
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