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Hi,
I have checked the timing reports and they are clean , yet when I do the gate level simulation with netlist and sdf , it is failing.
can anyone throw some light on this.
Hello all,
I am in urgent need of a test bench.
I have the verilog version of it. It would be of great help if anyone converts it into VHDL.
/***************************************************************************************
* TESTBENCH FOR SPI TO I2C
* January 2007...
A circuit with chain of inverters will only oscillate when the time period of the oscillation is equal to twice the propagation delay multiplied by the number of inverters chained, i..e. T = 2 Tp X N, factor of two is because a full cycle requires both - rise time and the fall time.
The above...
Where are you facing a problem? Designing a block in simulink or implementation of hdl code in ISE?
Can you please elaborate your objective in this project? I designed various filters using Matlab FDA-tool & system generator, so I think I can help you on this.
Greetings,
Why is the Power consumption in CPLD is 10 times more than FPGA , though the architecture is simple in CPLD & it is very complex in FPGA.
Thanks in Advance
I am not very sure about AMBA , but in i2C one can access only one slave per master at a time.
In AMBA AHB i believe the same case because unless one slave free the the data line the data can not be sent/receive at an instance.
Well its very obvious that (9999 downto 0) is not feasible by any means..
I dont want to implement this design - this is a question asked by a well known company in an interview
Thanks tricky for your reply,
Your suggestion is right but again (9 downto 0) gives me the dividend after 10th raising clock - I mentioned 10 as an example - the concatenation process has to be continued for a long time say 10000 clock or even more ..
Accept my apologies for that typo - I meant to say the dividend is increasing by 1 bit at every clock cycle where as the divisor is a constant - 2
Ex- say the dividend is 8 (3 bit) divisor is 2 i.e 8/2
next clock cycle it will be 15/2
next clock cycle it will be 31/2
next clock cycle it...
Thanks for replies, let me correct my statement .. :
I need to concatenate the input with the previous input i.e.
at raising_edge(clk)
a(n) & a(n-1);
at next raising it should be a(n+1) & a & a(n-1) and so on....
after every raising edge of the clock the divisor is increase by 1 bit. as the...
Hi Mike,
Thanks for your reply I checked your code - it works fine, but my problem is not just to check the divisibility by two ,
I need to concatenate the input with the previous input i.e.
at raising_edge(clk)
a(n) & a(n-1);
at next raising it should be a(n+1) & a & a(n-1) and so on...
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