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Recent content by shenghuo

  1. S

    how to build a blank zone

    i have embbed a symbol of black box module in top_level,but when synthesized always error happened. so i want to ask if black box module can be synthesized? thanks for ur helps
  2. S

    Help me solve an Ngdbuild error

    logical net 'modc_CS_IBUF' has multiple driver(s): pin O on block modc_CS_IBUF with type IBUF, pin PAD on block modc_CS_IBUF.PAD with type PAD how to solve it?:cry:
  3. S

    the question for the xilinx analyze

    I'm very grateful to get all ur helps.It is very encouraged when get a help in design difficulties.
  4. S

    the question for the xilinx analyze

    the error is inside port map. such as a=>b in instant1, c=>b in instant2, because i want to connect a to signal b,b also to c. but how to correct them?
  5. S

    the question for the xilinx analyze

    the error information as followed: logical net 'a_d' has multiple driver(s). I'd like to ask how can i solve it? thanks for ur reply.
  6. S

    question about ISE design

    thanks for all ur helps.
  7. S

    question about ISE design

    I met a problem that i cannot solve when i utilize xilinx ISE in my design. when analyze the top-level design,the error happens with followed information: No default binding for component: <memory_cntr>. Ports <EN_a,EN_b> do not match. Please tell me why. I have connected this 2 ports...
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