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place_opt does placement + optimization, so yes, it will add buffers in the design to fix design rule violations (max_cap, max_trans), add in buffertrees for high fanout nets, and to help fix timing violations
emresels looks good. heres my take at a gate level ...
input in
output out
input clk
flop (.D(input), .Q(flop_out) .CLK(clk));
xor (.A(input), .B(flop_out) .Z(out));
hi kornukhin
Thanks for the reply (and sorry for the delay). Not exactly what I was looking for, but a good idea which I hadn't thought of.
I have an sdc with all my input/output delays already set that I source in. What I was hoping to do was be able to relax them on the fly 10,20,30% etc...
Whats an easy way to query input/ouput delay values on ports in DC/ICC? I don't see an attribute for input/output delays on ports. I can get the vaules with get_timing_path attributes, but this takes to long if I want to loop over my thousands of ports. Anyone know an easier way?
fix the setup violation, then buffer the hold violation at the Q pin of the launching flop with the hold violation (or at least somewhere on the path not common to the setup violation)
This is assuming the violations are not from the same launching flops.
Hi,
I want to connect a 128 bit bus to the A pin of 128 different cells. Whats the best way to do this?
I can draw a wire from the bus to the pin on the 1st cell, create a label of bit<0>, and attach it to the wire. Then repeat for the other 127 bits ... yuk. How do I do this all at once...
Re: cksynthesis problem
you need to set an exclude point in your clock spec on the output of your mux to the long path (check manual for syntax). This way cts will not try to balence the two paths.
After scan insertion, the scan out pins of flops get directly connected to the scan in pin of the next flop. Since there is no logic in between, this can lead to hold time violations.
If you see these violations after synthesis, don't worry about them yet. They are normally fixed after clock...
set_output_delay -min 16 -clock I_CLK {i_clk} may fix it but I don't think set_output_delay is the proper way to constraint output clock (its usually for data paths and not clock paths). If you have a certain timing to the output you have to meet you can use set_max_delay/set_min_delay
report_timing
report_timing shows the most critical path (it may show the most critical path for each clock group)
critical path is defined as worst negative slack, which is the difference between data required and arrival time. When you time with latchs, time borrowing may happen and your...
1) hold violations are fixed post CTS
2) make sure your clocks are faily balanced on the paths you are fixing. If so add buffers to fix the violations
3) if your scan domain crosses multiple asynchronous functional clock domains you may need to redo CTS with these domains balanced -or- rodo...
I haven't done CTS at multiple corner but I would assume its due to skew variation as you mentioned. Skew can vary across corners because metals and transistors scale differently. ex. from bcs to wcs corner your net delays may scale by 3x while your cell delays scale by 2.5x ( i made these...
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