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If you know how setup time of a cell is calculated, i mean on which basis setup time of a cell is defined, then you can get that answer easily..try it...
Obviously, they will definitely effect the setup and hold times of a cell, a particular cell will have different setup and hold values for different operation conditions (Voltage, Temperature)..
Hi irfan
exactly what was krishna said is correct, first practise on flops and latches timing diagram..
one best solution is try to write characteristic tables for the timing diagrams and from that tables you can draw the circuit level diagrams..
Hi bala,
in front end stage
Logic Libraries.
Technology Libraries
Target Library (from where tool will directly pick the components)
Link Library (which is used to resolve the references in our design)
Symbol Library
Synthetic Library (like adders, multipliers, etc..)
GTECH Libraries (Which...
Hi, subhash, i think increasing the size of reg in reg-mem path will cause to decrease the setup violations, and one more solution is use lvt cells to improve its switching speed which will cause to decrease the delay...i hope its helpful..
ya..exactly what says by jaya sree..false path will not effect the timing but it can creates cross talk issues..so tool will do si analysis including false paths..
@haykp
in above i think the case you mentioned (@ negedge reset, if (reset == 1)) is never happens..
correct example is
always @(reset)
begin
if (reset == 1)
**reset the circuit**
else
**functionality**
for asynchronous with clock, you should not include the clock in always block
correct me...
Hi renoz
Two signals are said to be synchronous if they have certain timing relationship between them else we can say they are asynchronous..similarly in a design if output is sensitive of another signal(clock) then we can say that design is synchronous design. for example if you consider a fifo...
In such case we use high drive strength buffers which will be helpful in reducing slew rate(0-1 or 1-0 transition time), because in such buffers drain and source widths will be increased compared to normal cells, then those cells will drive high currents..hope you understand
in verilog all the statements are executed at same time, that's the main special feature of that..here in your example you are using blocking and non blocking statements..
actually verilog code is executed in four quarter cycles
1. all the blocking and non-blocking statements of rhs are...
For setup, OCV uses SLOW slews for the launch path, and FAST slews for capture path, where as for hold it's the opposite i.e. fast slews for launch and slow slews for capture..
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