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Recent content by Shanthanayaki

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    divide the clock frequency by 2

    Hi, But that is the clk divider by 2, and the frequency is divide by 2. We want here the frequency multiplier right. Somehow I am confused between the 2 circuits. Shantha Added after 19 minutes: Hi, I am sorry, I rephrase the question, simple circuit based on combinational logic to double...
  2. S

    divide the clock frequency by 2

    Hi all. Can anyone tell a way to design a circuit that can divide the clock frequency by 2. I am using XOR gate but cannot get it right. Shantha
  3. S

    Question on Digital design

    Hi everyone, What kind of combinational logic can be used to double the output frequency. I tried the one form this website, https://www.hitequest.com/Hardware/a6.htm but it doesn\'t work for me. Can anyone help ?. Thanks, Shantha
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    How to calculate the depth of a FIFO?

    Hi, Can anyone tell me how to calculate the depth of a FIFO. Usually the read cycle should be faster than the write cycle, to avoid overflow. Is the delay calculated on this basis. In many websites, they say depth can be 1,2, 16. But no where a clear explanation exists. Thanks, Shantha
  5. S

    why does NMOS pass a strong logic 0 and a weak logic 1

    nmos weak 1 Hi, Thanks. Appreciate the help Shantha
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    why does NMOS pass a strong logic 0 and a weak logic 1

    pmos weak 0 Hello everybody , Can anyone tell me, why NMOS pass a strong logic 0 and a weak logic 1 ?. Vice versa why PMOS pass a strong logic 1 and a weak logic 0 ?. Thanks, Shantha
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