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Hi,
Have you tried using below for defining resets in Spyglass DFT?
reset -name "scan_rstn" -value 0
test_mode -name "scan_rstn" -value 1 -scanshift'
Hope it helps!
-Shalin
Hi,
How does sequential depth appears in waveform during simulation?
For example, If my design has sequential depth equals to 3(no. of non-scan cells), then how will be the capture clock wave-forms for the stuck-at patterns? Will there be 3 capture pulses in capture window?
I understand ATPG...
Hello,
It depends on how many X-mismatches(exp=0/1 got=x) are there?
If they are huge,then check whether clock is propagating to that cell or not ; check whether cell gets initial reset or not. These are most possible reasons I have seen for getting X-mismatches.
In case it isn't clock/reset...
Hi All,
Just for curiosity, I wanted to know how to differentiate stuck-at faults generated from TR patterns.
Now, I am able to get list of the stuck-at faults targeted by transition fault patterns using the steps below.
1.Generate TR patterns. //Fault model - transition.
2.Write faults -all...
For IO testing we do boundary scan also known as JTAG(IEEE 1149.1 standard). This includes EXTEST which test the I/O's as well as the logic between two blocks.
One more method is to use NAND tree test for IO testing which includes the insertion of NAND tree structure at all IO pads on the...
Can you clarify what do you want to generate? Mux is to select either A or B input.So, you will get either High or Low frequency clock based on selection line.
In launch on capture(LOC) waveforms, what is the significance of applying dead/wait cycles before capture pulse and after last shift when scan enable is low?
Is it only because to make Scan Enable signal transit to low properly?
I heard that min. 2 dead cycles are required after shifting, for...
According to me,when you are running simulation for design in standard mode(Non-compression mode),you may run whichever(serial/parallel) simulation you want to according to your total simulation timeline.
Till now, i came to know that when we are using compression mode, simulation in parallel...
Hi,
No,its not design or setup error.Its an output mismatch error.
Simulator is displaying error like got ? expected 1/0. Serial simulation is successfully passing for all the patterns.Only parallel simulation is failing.
Hi Ranjit,
As dpaul mentioned, Setup/Hold violations are fixed by design engineers,i don't think you need to care about it as we are doing pattern simulation without timing check.
If you are talking about serial/parallel simulation then, let me take you in some deep,
In serial simulation...
Hi all,
I want to know that in compression mode why i am getting simulation failure if i use parallel simulation?
As i jump to serial simulation, it is successfully passing the pattern simulation. What could be the reason? Does parallel simulation in compressed mode bypassing something because...
As per my knowledge, most possible reason for output miscompare could be due to the design consructs that are not matching with application of STIL data.While doing simulation, I have faced this miscompare errors many often, and it was because of the constraints on clock(In my case) which was...
After you have generated patterns for your design, all you need to do to is pattern simulation to verify your patterns.
Now,answering your first question,
For debugging output mismatch error you need to read "TEST PATTERN VALIDATION" by Synopsis user-guide.
In that you'll find there are six...
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