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lurchman
thanks for your answers,now i understand that z^-1 is a DFF block and 1-z^-1 equals accumulator after reviewing the singal process textbook, so far i still don't understand how to calculate the bit width exactly,the input bit width k can be deduced by minimum frequency precision which...
this DSM is used in a fractional-N PLL,but i dont know how to translate the signal flow graph to real circuit like the second picture,another question is how to determine the bit width of the input and output data,thx!
the picture above is a classical bandgap structure,the purpose of OP is trying to make Vx and Vy equal,so my problem is could the passive port and the negative port of the OP be exchanged?WHY?
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