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I will be tgreatful if you help me, I am almost done with my coding but the big problem is the fpga board could you help in any way, I'm kind of stuck right now
i'm using hard decision, my problem is in coding part how to write the code to compare my recievede code with state output and calculate the ham distance , for now I need to solve how to write the code to calculate the hamming distance this the code i write to start up for branchmetric
LIBRARY...
decoder vhdl
hello every one
I am doing viterbi decoder with vhdl k=3 r=1/2 I have done the encoder part of it and I am middle of deocder I have problem for codding the hamming distance should I do it in trellis codes or branchmertic code can any ine help me please.
thank you in advance
vhdl decoder
could any one help to write my code in vhdl for viterbi decoder 1/2 rate with constraint length 3 I did some coding for a start but I'm not sure is it correct or not
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity...
No I didnt ask to do design for me I;m half way with my design and done the convo encoder and I aldo did the matlab , I need the codes to compare with my codes because I'm stuck in somewhere, by the way if you cant help don't reply....
how to design viterbi decoder
hello
I'm doing my final year project design and implementation of virebi deocder, can any one can help me with a source code , I'm using VHDL
viterbi vhdl
thank you haneet , I have basic problem I dont know how to start , I know that I have to use convolutional code and trellis diagram but how to start ? its a bit complicated
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