Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
mcs8140
I am using moschip 8140 network usb processor board.Through serial port I connected to windows I am visible to see board linux in hyper terminal.
I have to execute c programs in board linux.in mcs8140 ARm 926ejs processor.
while Iam compiling cc filename.c or gcc filename.c...
vlsi is having future in two years or not
I feel that VLSI has good future compared to any other field..
my reasoning goes like this..
Most of the products we daily use, will be converted to
electronic good...
Mean all the products will have some form or the other kind of
IC chip embedded in...
verilog include file
For including a file in verlog, i used `include in a test module. So my aim
was to call the tasks that are defined in the file 'include "task_def.v"
while compliling, i have tried compiling both the test module and task_dev.v
Modelsim is reporting lots of errors for the...
Yes, Functional coverage.
Added after 2 minutes:
Can you tell me what kind of coverage scenarios are possible for hub ?
i could see all the hub specific standard requests.
What else could be there?
Re: USB HUB
Hi spbshankar,
As seen from ur post, i think that you have better USB know how. Can you plz reply my querry posted on 24 th april, related to USB + UTMI specs understanding.
Thanks
Senthil
Re: Verification IP
A verification ip contains some components, which are useful in tesing a design. ( say USB 2.0 or PCIX) .
It contains Stimulus generator that is capable of generating tests (phase level, transfer level etc), coverage collector (to see whether all the tests have been...
I am going through the UTMI specs Version 1.05. On page 22 of UTMI specs, it was told that
"
1. FS ONLY implementation of the UTM would provide 32 CLK cycles per byte time.
2. LS ONLY implementation of the UTM would provide 32 CLK cycles per byte time. "
But in the page 25, it was written that...
Hi Folks,
This is a sort of general question.
Like if a person has filed a patent and it is sanctioned. How much money he can approximately get ?
I know that it lot depends on the area of the patent which he filed on.
If it is in company, like i m in a vlsi company. I was told if i file a patent...
Hello ,
I have some doubt regarding, effect of loop gain control over stability of Opamp.
Normally if we take a correctly designed single ended opamp, it has a one dominant pole, and nondominant pole after unity gan frequeny and a right half zero at twice that non dominant pole.
we ll take two...
Opamp stabilty
Hello ,
I have some doubt regarding, effect of loop gain control over stability of Opamp.
Normally if we take a correctly designed single ended opamp, it has a one dominant pole, and nondominant pole after unity gan frequeny and a right half zero at twice that non dominant pole...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
