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Recent content by secondlife

  1. S

    urgent help on ncsim error required..

    ncsim: *F,VIFCRF (/project/../../): Virtual interface reference was compiled for width=1 but has actual width=6 in interface instance ips_if. what to do...i am usiing ncsim
  2. S

    non blocking assignment on the same clock...

    can there be any scenario, where assignment and evaluation happens on the same clock edge in nonblocking assignment?
  3. S

    nokia application development

    hi i am a novice to application development for nokia phones (N73) based on symbian OS v9.3 on S60 SDK.I have all the documents from nokia forum site...but still i am not getting the clue how to make a c++ application for the above .what are the steps involved?how to start?
  4. S

    breakdown voltage vs. doping level.

    I hope you must go for Milliman & Halkias(yellow one). I dont remember the chapter exactly but ithink its second or third..all your doubts will be cleared.
  5. S

    eference b/w forcing and configuring

    What will be the deference if i directly force a value on the output of a device with "force" in verilog vs if i configure my device to get the same output.
  6. S

    The bjt and cmos process

    go for combination of both as per the staged requirement.
  7. S

    Questions about poly layer in CMOS layout

    Re: CMOS layout? 1.As poly create parasitic transistors and have higher resistivity then metal ,conectivity by metal is preferable but for very short distance there is no as such problem for connecting by poly. 2.Your question regarding gaurd ring is much serious when u r doing analog layout...
  8. S

    design of buffered opamp

    i wanna design buffered CMOS opamp with specs DC gain 80db UGB 10MHz Slew rate 5v/50ns ICMR -1 t0 +1 VDD(VSS) 2.5(-2.5) CMRR should be high as much as possible PSRR should also be as above.. above given are the main constraints. CL=10pf RL=2kohm i wanna design as soon as possible.
  9. S

    architecture choice for 24 bit ,1Khz DAC

    at very first i would like to say that you have not goven the specs in totality..next thin blind faith in sigma delta doesnt worth as you just want to work on 1Khz it will be better to devide your design in thermometer coded then r-2r ladder and then some lsbs for current steering or any other...
  10. S

    What is the easiest to learn: ADC/DAC, filter, PLL or layout?

    Re: need some advice first thing is that adc and dac are two different topics and next thing is that for entering in company you need just good fundamentals nothing else...just be familiar to thjis tpic is more then that...even then if u want you can go for DAc or pll..all the best
  11. S

    swithing between unipolar and bipolar

    How can a circuit be made ,say for DAC, so that it can work in both bipolar and unipolar mode by switching from one mode to another?
  12. S

    Who to map modulators +/- output in VHDL?

    Re: VHDL question for the first two questions first it is better to go for a 2s complement representation and representing the number in binary format even if they are negative.
  13. S

    architecture choice for 24 bit ,1Khz DAC

    you will have to opt for a hybrid architecture...for 24 bit you can not go for a single architecture for all bits.
  14. S

    Looking for "Design and test of integrated inductors for Rf application"

    where can i get the book"Design and test of integrated inductors for Rf application" By Jaime Aguilera and Rac Berenguer.......i need it very urgent...plz help
  15. S

    What's so important about DigiTrim?

    What's so important about DigiTrim? There are lots of other trim methods.

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