Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by sdedov

  1. S

    performance degrades a lot in extracted simulation

    Hi, encrypted rule file is an issue... I'm afraid that there is no other way for you than to check extracted netlist manually. First check if the netlist contains "noconn_..." net names - sometimes Calibre "cut" nets during R extraction. Second, try to use output netlist reduction (Tacer for...
  2. S

    performance degrades a lot in extracted simulation

    Hi, In the older versions of Calibre (before 2005) the following issue is appeared: during the PEX Netlist Distributed (R+C,CC,...) extraction the parallel branches of conductor could be broken thus often making the resistive path falsely long (especially for supply/groung). It could cause the...
  3. S

    Save Analog input (at clock frquency) to Text File using Verilog-A

    Hi, Try to use $realtime function, for example. Or See "Cadence Verilog-A Language Reference" - "Examples of $strobe Formatting"
  4. S

    Save Analog input (at clock frquency) to Text File using Verilog-A

    Hello, First you should create symbol in Cadence. Period and toff became the parameters which you should define in your schematic. Thus you catch the sample at time defined by this two parameters. You samples voltage between ps and ns pins (i.e. for single-ended ns should be connected to 0). At...
  5. S

    Save Analog input (at clock frquency) to Text File using Verilog-A

    Something like this: `include "disciplines.vams" `include "constants.vams" module sampler (ps, ns); parameter real period=1 from (0:inf); // sampling period (s) parameter real toff=0 from [0:inf); // offset time for sampling (s) input ps, ns; voltage ps, ns; // input port...
  6. S

    not able to make layout in cadence

    Check if your design is attached to the technology library.
  7. S

    what are Multicut vias & advantage of it?

    Your technology/PDK supplier should provide you with such information. Usually this data is placed in the "Design Rules" papers. You can find couple/fringe capacitance and resistance information for each layer/interlayer. Some fabs also provide with the Kelvin contact res vs current info.
  8. S

    What is mean by Retrograde Well ?

    Try to look at **broken link removed**
  9. S

    set up time calculation for delay linearization of D-latch for look up table method

    It would be nice if you send your circuit. In theory setup/hold should not depend on output load because it's mainly defined by switch (if you use switches).
  10. S

    [SOLVED] very weird calibre view parasitic simulation

    I'm late but couple remarks anyway: As said above the problem could be in the pin order of subckt definition/call. - if you are using Cadence schematic view to the netlist extraction for Calibre you should be so careful with the subcircuits CDF properties like pin order. Try to check if this...
  11. S

    Change the model of a transistor

    Did you try to change CDF properties of your device? CIW->Tools->CDF->Edit->lib/device name and change model name...
  12. S

    [SOLVED] very weird calibre view parasitic simulation

    Try to check if the "Output looped resistance to RC netlist" is switched on. (PEX Options -> Netlist)
  13. S

    180nm denotes which one Poly width or min diffusion width ?

    Usually it's a channel length, i.e. Poly width.
  14. S

    Calibre RC extraction

    In my version of Calibre: PEX->Outputs->Extract parasitics for specified nets->(Top or Recursive Nets)->Include. Fill the list with the required net names. ---------- Post added at 10:55 ---------- Previous post was at 10:49 ---------- This is not quite correct: if you use distributed RC...

Part and Inventory Search

Back
Top