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Recent content by satty_008

  1. S

    Is it possible to program a zigbee module as a modem without a UART.

    I have a zigbee(XBee) module and i want to program it as a modem because my project deals with RSSI. Can anyone please tell me how to cofigure a xbee module as a modem and my main problem is that the board that I am using does not have a slot provided for xbee (MCB 2300 with lpc 2378) all I...
  2. S

    difference between conv_integer and to_integer

    Type conversion is a regular operation that is performed while writing VHDL code, but it can sometimes be cumbersome to perform properly. An example of this is converting STD_LOGIC_VECTOR types to Integer types. You now have the following options to perform the same: Function "conv_integer"...
  3. S

    Non synchronized next state and current state in uart receiver!! VHDL

    LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; -- Serial UART receiver entity uart_receiver is generic ( WIDTH_1 : natural := 4 ); port ( CLK : in std_logic; -- Clock RST : in...
  4. S

    Problem with assigning a generic

    Thanks a lot.. so you mean to say there is no way other than to assign a constant to generic ? :?::|:-(
  5. S

    Problem with assigning a generic

    I am relatively new to VHDL and am facing problems with generics. I want to assign a signal value to a generic . Is it possible? architecture rtl of entity_name is signal ibaudratetop: integer; component my_baud1 is generic( baudrate : integer := 115200; clock_freq_mhz ...
  6. S

    Syntax Problem in VHDL

    Hii , I am an amateur in vhdl.I was referring a UART code and I came across this line "iCount /= SIZE" can some one please explain what it means and how it is manipulated? SIZE is defined as 4 in generic and icount is a signal which ranges from 0 to SIZE
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    Problem with UART. Need to test UART with variable baud rate on altera de2 115 board

    Thank you... That was helpful.. :):-) could you also please tell me what is meant by oversampling ?
  8. S

    Problem with UART. Need to test UART with variable baud rate on altera de2 115 board

    Problem with UART code in VHDL... Please Help process (rst, clk, cycle_wait) variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); begin if rst = '1' then wait_clk_cycles := (others => '0')...
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