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Recent content by Sasi Cm

  1. S

    Genetic algorithm in vlsi testing

    I want to know that, is there is any genetic algorithm technique applied in the test data compression technique or test data encoding scheme.... If yes means pls i want to know that technique..
  2. S

    doubt in module port map.

    but i wrote these encoder and decoder as different programs...
  3. S

    doubt in module port map.

    Doubt in port mapping: How to port map the following module in Verilog. The encoder has the input as x[120:0] and output as y[55:0]. Now the decoder obtain the input from encoder by port mapping. The decoder has the input as a[55:0] and output as b[125:0]. Now how to port map the y and b.
  4. S

    Need bench mark circuit

    Where to download the benchmark circuit S5378,and S9234 for verilog??
  5. S

    Need Definition friends....

    Thanks..And i want to know that for every clock cycle there is a 35 input and 49 output.?
  6. S

    Need Definition friends....

    I want to know what is a bench mark circuit..? How to give the inputs to a benchmark circuit.? And how many inputs are there for the benchmark circuit S5378..?
  7. S

    [SOLVED] Is this possible in xilinx..?

    module encc(a,b,c,clk,temp); input [0:50]a; input clk; output [0:25]b; reg [0:25]b; output [0:4]temp; assign c=a[0:4]; always @ (posedge clk) begin assign temp=c^a[5:9]; if(temp[0]!=1&&temp[1]!=1&&temp[2]!=1&&temp[3]!=1&&temp[4]!=1) begin c<=00; end else...
  8. S

    How to Resolve this for loop error..

    I have to say thanks for ur help....Really Thanks...... For example only i say four bits..the no. of bits r not a matter... its simple for small length of sequence. In case of long length ,(range of 500 bits ) how can do these comparison. So i try the for loop. But its not working. Other wise i...
  9. S

    How to Resolve this for loop error..

    i try to do the following... i have a length of sequence..Ex:1010 1110 1011 0001 1001 ........ now i save the first four bit as constant and i have to compare it with all remaining bits... if both are eq,then i get output as 00,complement means 10 and neither eq nor complement means 11...
  10. S

    How to Resolve this for loop error..

    it says that it is not possible to use a variable in the for loop....
  11. S

    How to Resolve this for loop error..

    module encc(a,b,c,clk,temp); input [0:499]a; input clk; output [0:4]temp; reg [0:4]temp; output [0:4]b; output [0:1]c; reg [0:4]b; reg [0:1]c; integer m,n; always @ (a) assign b=a[0:4]; always @ (posedge clk) begin for(n=5;n<=499;n=n+5) begin for(m=9;m<=499;m=m+5) begin assign temp=b^a[5:10]...
  12. S

    what this error means....?plz....

    module compare(a,b,out0,out1,out2,temp,temp1,temp2); input [0:19]a; output [0:4]b; //reg [0:4]b; output [0:1]out0,out1,out2; reg [0:1]out0,out1,out2; output [0:4] temp,temp1,temp2; reg [0:4] temp,temp1,temp2; always @(a) begin assign b[0:4]=a[0:4]; assign temp=b[0:4]^a[5:9]...
  13. S

    what this error means....?plz....

    assign b[0:4]=a[0:4]; for this line i get this folloeing error. # ERROR: compare.v(12): LHS in force may not be a net: b
  14. S

    How to assign value to b,plz....

    module compare(a,out0,out1,out2,temp,temp1,temp2); input [0:19]a; wire [0:4]b; output [0:1]out0,out1,out2; reg [0:1]out0,out1,out2; output [0:4] temp,temp1,temp2; reg [0:4] temp,temp1,temp2; always @(a) begin assign b[0:4]=a[0:4]; assign temp=b[0:4]^a[5:9]...
  15. S

    need help in lfsr project

    sorry...i cant understand what you are saying... is that possible to do this....?
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