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Recent content by sanju_

  1. sanju_

    Best VLSI Job websites

    Hi, https://jobs.siliconindia.com You need to update twice a day in all website if you are actively looking for a job. morning before 9 and afternoon around 2/3 daily.
  2. sanju_

    Best VLSI Job websites

    Hi, look in monster jobs www.monsterindia.com best for vlsi
  3. sanju_

    Verilog HDL - Book Recommendations

    Principles of VLSI RTL Design A Practical Guide by Sanjay Churiwala -- > Advance level Ensuring RTL intent Creating simulation-friendly RTL Creating timing-analysis-friendly RTL Creating clock-domain-crossing (CDC) RTL Creating power-friendly RTL Creating DFT-friendly RTL Creating...
  4. sanju_

    FIFO depth for async FIFO

    https://www.fullchipdesign.com/fifo_depth_formula_calculation.htm
  5. sanju_

    various error in programming with vhdl

    Hi, In addition to FvM suggestion Remove twice declared CS in signals(remove one cs ) signal da,cs : std_logic_vector(31 downto 0); signal cs,m3 : std_logic_vector(31 downto 0); and add encdec signal
  6. sanju_

    about mini project

    fpga4fun.com - Welcome front end
  7. sanju_

    difference between VHDL and verilog HDL

    try googling you will get lot of answers.. some of them i know is for beginners verilog is easier than vhdl. in verilog no library is attached but in vhdl you need to attach library. Hdl Programming Vhdl And Verilog - Nazeih M. Botros - Google Books ---> refer page 32
  8. sanju_

    wipro VLSI job suggestion

    still now no one sent out...
  9. sanju_

    Verilog FAQ

    i got job on electronics because of this site... all my interview questions on this site itself... :)
  10. sanju_

    i wanna learn TCL can any one help (and may be PERL too)

    Tcl Tutorial
  11. sanju_

    All about VLSI Physical Design Stuff.

    **broken link removed**
  12. sanju_

    fsm states not displaying

    Hi, define clock in your test bench and try... no clock is running so it wont see the rising_edge(clk)..
  13. sanju_

    wipro VLSI job suggestion

    Hi, you will be getting around 17k-18k in hand's at starting to end of year increments calculated according to performance, i have seen 4-5 people getting 30% of their normal salary in wipro vlsi
  14. sanju_

    Basics of VHDL programming

    https://www.edaboard.com/threads/19712/ **broken link removed**
  15. sanju_

    online FPGA news, tutorial, howtos etc. sources

    Basic FPGA Tutorial
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