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Hi im trying to convert a matlab code to HDL using HDL coder, the code gives me floating point output.
after getting the HDL code, when i m trying to synthesize it, it gives me an error that floating data is not synthesizable? can anyone tell me that di i need to convert my data to some other...
I'm designing a structure in VHDL with clock. the design is getting simulated and giving me the correct output but when i synthesise that code, i get the following information regarding delay.
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output...
hi
i m designing a bypassing multiplier. nd in this by checking the multipler bit, we can bypass a particular row or clumn so as to reduce switching activity. but in verilog, conditional use of generate statement is not being supported for bypassing. the reason is while elaborations, we cant...
i'm comparing four multipliers for delay,area nd power. wht shud be the max frequency to be given as design constraint for good performance of the multipliers. i'm using Xilinx9.2 nd comparing array,modified booth,wallace tree nd combined booth wallace
waiting for ur valuable suggestions
thanx:|
i'm designing an interrupt controller in verilog. the problem i'm facing is when our first interrupt acknowledgement (inta)signal comes, we'll write data on data bus. when 2nd inta comes another data shud be written nd similarly for the third inta. nw the point is how to check three pulses...
hello!
i'm doing my thesis on comparison of multipliers. nd i'm over wid the codes of booth, wallace and booth encoded wallace tree multiplier and calculated their delay nd the delay comes out is least for booth encoded wallace tree multiplier and for the multiplication of two 8-bit signed...
hi
i want to ask if verilog language support the multiplication operator for bit_vector, integers. then what is the fun of making new architectures of multipliers(booth,braun,wallace,dadda)like this.
hi. i'm not getting the combinational delay of the circuit bt the benefit i got by using this latch is that the dely has been reduced from 27 to 20 ns.
here r the results i'm getting after synthesis.
Minimum period: 20.138ns (Maximum Frequency: 49.657MHz)
Minimum input arrival time before...
hi
Again Thanku for a quick reply. i have added clk in my module then i synthesised nd place &route the design. loaded both the files . Then i checked aynchronous delay report nd clock region repot.
the report i'm getting shows that there are 20 worst net delays. in synthesis report i'm gettig...
Thanx for a quick response. Bt i have nt added clk in my major block. If i take into account the clock. the result i'm getting after synthesis is that only the setup nd hold time of the whole unit. nt the combinational dely. Actually i'm new to Xilinx also. i'm learning that also side by side...
latch multiplier
hi. i'm doing comparison of booth, wallace nd their combination i.e booth encoded wallace tree multiplier in veriog. i'm over wid the coding nd then wid synthesis. in synthesis i calculated the combinatiiomal delay of all three for the comparison purpose. nd getting least for...
hi. i'm doing comparison of booth, wallace nd their combination i.e booth encoded wallace tree multiplier in veriog. i'm over wid the coding nd then wid synthesis. in synthesis i calculated the combinatiiomal delay of all three for the comparison purpose. nd getting least for biooth encoded...
hi! i'm doing my masters thesis in multiplier. a combination of wallace and booth. will it be ok to do it for 4- bit or 8- bit? please suggest if you have more ideas.
thanku
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