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The traffic light controller should have 4 states in total:
at start , the green traffic light and the red footwalker light is active
when pushbutton is pressed the yellow light of traffic lights becomes active and the red footwalker light still remains active while the timer starts for 3...
I am trying to load my program to a Block RAM using Data2mem, after the bitfile is generated. Here are the steps:
I have generated a BLOCK RAM as single port ROM with 32 bit-width and 16384 bit-depth.
Then translated the design without any BMM file and looked at the PlanAhead tool to see which...
I have generated the following ram and rom from CoreGen:
component brom_im
port (
clka : IN std_logic;
addra: IN std_logic_VECTOR(15 DOWNTO 0);
douta: OUT std_logic_VECTOR(31 DOWNTO 0));
end component;
component bram_dm
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0)...
Dear ads-ee,
Thanks for your time. I have still some confusions. Hope to get more from you.
1.
You mean if there are multiple paths due to different clocks, I have to look for the path with from/to same clock with worst case slack is the critical path. But 8.607ns is also not within same clocks...
Thanks ads-ee,
But this line only indicates what is the minimum period as also shown in Timing Summary Section:
Minimum period is 25.219ns.
On the following lines from 760 onward there are some Paths, I think this values is coming from these paths somehow (is it true).
Which are the paths...
Dear All,
I have a design which uses a DCM to downscale my main clock to 5 more clocks. When I see the PAR timing report. It shows, different paths, how can I figure out that which path is actually is the critical path?
It also shows that:
Clock to Setup on destination clock clk_in...
Dear All,
Can you please guide how to find Peak Power in Xilinx 13.2. I can find the leakage and dynamic power using Xilinx Power Analyzer (XPA) with vcd file input. But could not find how to get the peak power?
In the previous versions the peak power was also available in XPA?
Please help...
Thanks alot dear. The
The calibre version is 2015-2016.
How to use the mgcld license server at <calibre_install_path>/pkgs/mgls/lib.
Should I use MGLS_LICENSE_FILE=<calibre_install_path>/pkgs/mgls/lib
Regards
Dear All,
I m trying to do DRC with Calibre in Virtuoso. But while doing Calibre>nmDRC, I m getting the following error:
// ERROR: The following products could not be licensed sufficiently:
// ERROR: - Calibre Interactive
Also when I type on command line, get the same response. Please guide...
1. For power estimation SAIF/VCD file is required, which is generated during ModelSim simulation. Before the simulation, I wrote a script to find all the FF and initialize them to a value. Still there is not 100% annotation.
2. In PrimeTime, as far as I studied, a synthesized netlist, library...
Thanks for the response dear dpaul. For a flattened design I can find the FF and initialize them. But still when try to do power estimation with PrimeTime it shows many not-annotated nets, I don't know the reason. With so many not-annotated net, still power estimation is right?
Hi All,
while doing power estimation after synthesis. i am getting not-annotated nets. How can we exactly map the names? How to solve this annotation problem?
The saif file is generated using Modelsim and synthesis file from design compiler.
Please help.
Regards
I synthesized Leon3 with two different options:
flatten-all & auto-ungroup:
It produce a single top level verlig module with all the module merged inside. During synthesis there are some uninitialized FF which cause 'x' propagation and results in incomplete annotation while doing power...
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