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Recent content by sagar_echip

  1. S

    Problem with Pole zero analysis using multisim

    When I tried to find input impedance function's pole zero of a parallel LC network using Multisim pole zero analysis, I get following message " ........... | | doAnalyses: matrix is singular | | | | | | pz simulation(s) aborted " The circuit as well as log file attached...
  2. S

    What is the minimum supply voltage for Op-amp IC 741

    op amp ic 741 What is the minimum supply voltage that can be applied to op-amp IC 741?
  3. S

    distance between nodes as in IEEE 802.3

    Why the distance between nodes is specified as 2.5m in IEEE 802.3?
  4. S

    how to test op-amp IC 741

    how to test op amp how to test op-amp IC 741? is it possible using IC tester?
  5. S

    suggest verilog based reference design

    verilog design concepts == modified message == pls. suggest me a verilog based reference design(project) which explains all the steps from specification to synthesis, for study purpose. any university site, lab notes also will serve the purpose. i know opencores.org thanks
  6. S

    suggest verilog based reference design

    verilog based project pls. suggest me a verilog based reference design(project) which explains all the steps from specification to synthesis, for study purpose. medium sized project in networking domain will be preferable i know opencores.org thanks
  7. S

    help ! analog and mixed signal design

    how does mixed signal design differ from analog design? how shjould i start studying mixed signal design?
  8. S

    The Ultimate Memory Guide by KINGSTON

    pls. suggest tutorial link which discuss fundamental working of SDRAM,EDO RAM, Dual port RAM and other differnent types of memory.
  9. S

    How to enter the field of Mixed Signal Design?

    Mixed Signal design pls let me know ;To enter mixed signal design field which topics,software one should know?
  10. S

    Hardware or Coding first?

    hi i read in one tutorial,u should know hardware/circuit first before starting coding. 1.Is this always possible ? 2.we get the required components after synthesis,so why should we think first about it? thanks
  11. S

    specifiation to synthesis

    pls. suggest any large,well illustrated, design example in verilog, in networking domain for study purpose. (from specifiation to synthesis) thanks
  12. S

    Verilog Code for Ethernet controller

    verilog ethernet Can somebody guide me from where to find free Verilog Code for Ethernet controller
  13. S

    Looking for entry level job in ASIC design

    help for project hello i know verilog well and have xilinx foundation on my pc at home. i am searching for entry level job in asic design. pls. suggest me a project in networking domain and some info regarding it so that i can do it on my own and include it in my biodata. thanks
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