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Design compiler has its own *more primitive* timing engine called design time - which is essentially a poorman version of Primetime. It is used mainly for synthesis and timing check only if you do not have Primetime.
Primetime on the other hand is a signoff timing tool - mainly you signoff your...
On chip PLL
AT-speed-testing means running scan capture at the functional clock freq.
This is also referred to as AC scan, as opposed to normal scan where you run your scan shift/capture at a reduced freq. (scan clk provided by ATE - PLL bypassed)
at-speed test allows you to detect additional...
spef primetime
generally, when reading SPEF, the STA tool does an internal RC extraction before processing with timing calculation. In certain instances, some clock transitions may be modelled ideal if the clocks are defined on output pins(see solvnet). Reading SDF is more straight forward and...
Generally depending if you are in test design or test development.
(tasks are interchangable depending on company)
test design>>
Test structure definition and specification
implementation of DFT (scan, BIST, boundary scan, macro test, etc)
ATP generation
pattern simulation
test development>>...
synplify lib2syn
I am considering using synplicity over DC, but my asic library only provides .db or .lib format. Also what are the usual trip overs when one switches from DC to synplicity? As I am new to synplicity, appreciate if someone can advise...Thanks!
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