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Recent content by rvkei11

  1. R

    SPI communication Debug

    Hi all, I think in SPI there is no acknowledge bit. How we can ensure the data is written in the slave? Thanks in advance
  2. R

    How many records can be stored in 24C512 EEPROM ?

    Hi all, I interfaced the 24C512 EEPROM, with my controller. I want to store a 16 digit character string in the EEPROM(Single record). It is organized as 65536 words of 8 bits. How many records i can store it? Any efficient methods are there to store and retirve? Thanks in advance.
  3. R

    Difference between debugger and emulator

    Can any one differentiate the debugger and emulator?
  4. R

    Looking for timing diagram tool for drawing the waveform signals

    Hi, Can anyone suggest a good timing diagram tool to draw the wave form signals.
  5. R

    verilog code synthesis

    I want to do the image processing, Array[row][col] of 8 bits then want to process in matrix format. Think if we written the code it will simulate but will not synthesis...
  6. R

    verilog code synthesis

    Thank you...Can you please tell in verilog reg[8:0]array[8:0][8:0] is synthesisable?
  7. R

    verilog code synthesis

    I think reg [8:0]array[8:0] is synthesisable.... This is eight bit array element...am i right?
  8. R

    Can you instantiate a module within a function in Verilog?

    In verilog RTL approach , Is it possible to instantiate a module within a function?
  9. R

    verilog code synthesis

    Can anyone tell, two dimensional array is synthesisable?
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