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Hi all,
I used synopsys nanosim to simulate verilog netlist. The verilog netlist is generated from DC. But when I run the nanosim, the segmentation faults came out. What are these faults mean? How can I solve these??
Thanks for any help!!!
Hi all,
I'm a student learning to use Cadence SOC Encounter to generate necessary files which will be used in Nanosim simulation. I can get the verilog netlist file and .spef after P&R using encounter. How can I get the SPICE models file(.mod) ? Do I need some other files when I'm going to use...
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