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Re: Clocks problem
In a design that only uses one edge of the clock(either falling or rising), duty cycle is not important. Otherwise, you have to make sure no setup/hold is violated between FFs of different clocking edge.
Net delay is determined by the RC of that net. Ther are three model to use :
1. best case : no delay, 2. typical: balanced tree, 3. worst: lumped.PT use the back-annotated parasitic file to calculate net delay according to the model you choose.
It's a logical path in you circuit and that path will not be exercised in your logic function. Or the path between two clock domains is also considered false path.
asic vs. fpga
FPGA sythesis is much more easier than ASIC.
In FPGA synthesis tool, like Synplify, you just specify FPGA vendor and model of the chip, than done !
You can create a spare gate module and instantiate it in other modules in upper level.
But you need to tie at least one signal to this spare gate I/O port.
Remember set_dont_touch to this module in DC.
how to use maxskew constraint
I have a low end FPGA which has no PLL or DLL.
Is it possible just to use digital gate to implement DLL function ?
Is DLL all digital circuit ?
Unit delay question !
When simulating the netlist generated by systhesis tool, there is a unit delay used in timing. What's this unit delay ? Why not just use the timing generated by wire load model ?
Thanks !
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