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Recent content by Rohitchampion

  1. R

    Problem with Spectre in Cadence Vitruoso

    Did you click on 'Check and Save' button before running circuit? I think running circuit without checking and saving gives that error, I am not sure though.
  2. R

    ALU design in VERILOG

    okay. Then it's very easy. You need not create all those modules separately. just give cases as 3'b000: output = a+b; 3'b001: output = a>>1; blah blah blah
  3. R

    ALU design in VERILOG

    Ah, Sorry, I didn't see that. And I am not getting your exact question. Can you please describe about your ALU and it's functioning(its operations) so that I can get your question?
  4. R

    ALU design in VERILOG

    I am posting one example here. verilog code for 4-bit full adder. module half_adder (output s,c, input x,y); //1-bit half adder xor(s,x,y); and(c,x,y); endmodule module full_adder (output s,c, input x,y,cin); //1-bit full adder wire s1,c1,c2; half_adder ha1(s1,c1,x,y); half_adder...
  5. R

    ALU design in VERILOG

    You just have to call all those modules you have created in your main module(you have named it 'alu' i guess). I hope you know calling one module in another module.
  6. R

    [SOLVED] 10101 non-overlap sequence detector

    Yeah, and there's nothing like same state cannot be assigned twice or so. where would be state transition if input is 1 in state B or 0 in state C etc ? While drawing state diagram, take all possible cases into consideration, that would help you in complex problems for reducing circuit.
  7. R

    address and data lines

    Question is bit unclear. what do you mean by 3 bit each? did you mean each location stores 3 bits of data? By the way, for 2M locations, there will be 'n' address lines, where 2^n = 2M And for 3 bits of data i guess there would be 3 data lines.
  8. R

    [SOLVED] 10101 non-overlap sequence detector

    As you are designing non-overlapping sequence detector, if circuit is in E state and it gets input 0, it will go to state A with output being 0. You will write it as 0/0. Do you need any other help with state machines? All the best!
  9. R

    why we used different modeling to write verilog code

    You will come to know about all these things as you get more into it. All the best!
  10. R

    Reset conditon for logic

    Reset, as name says, is used to bring circuit to required initial state, i.e. to reset circuit to. What do you mean by
  11. R

    why we used different modeling to write verilog code

    There are not specific rules for when to use which modelling. You can use any modelling type as per your needs, or even hybrid modelling too. Usually we use behavioral modelling for sequential circuits and structural for combinational circuits.
  12. R

    source and sink current

    https://bit.ly/1l3lKml All the best!
  13. R

    digital design from Timing diagram

    It depends on whether you want synchronous circuit or asynchronous one. And there are many techniques to design it. In synchronous you may first draw state diagram (moore or mealy), then according to flip flop conditions you may proceed (state assignment, nest states, equations etc). In...
  14. R

    Verilog hdl code 1hz

    What exactly you didn't understand in this code? Are you familiar with verilog syntax and logic?
  15. R

    multiplexers for implementation of logic gates

    Google it.. There's a lot of information available.
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