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Recent content by rocal

  1. R

    What will be the directions of 100 pins in a chip during shift mode?

    Re: DFT Input pad as input, output pad as output, in general.
  2. R

    Need fundamentals of SDRAM controller

    Re: Hi where can I get the simulation models you mentioned.
  3. R

    How to implement DFT with single scan clock

    Of coure, the MUX inserting for clock selection must be done. But many timing problem must be considered, when you just use one only clock.
  4. R

    Does the architecture of the design change after synthesis?

    Re: Synthesis The goal of synthesis is to changing the RTL sources to gate level netlist. You write what you want. Of course you can see the "architecture" (sorry I am not sure what you exactly mean) in the target netlist.
  5. R

    about ASIC verification

    writing_testbenches_2rd.rar?? R U sure? I wonder it is for the systemverilog.
  6. R

    What exactly is SERDES?

    I am just a digital design engineer. So my question: WHAT IS SERDES? Thank you. Very much.
  7. R

    about ASIC verification

    Hello guys, I think I am a fresh verification engineer with poor skills. :( I want to know your comments about the book Writing Testbenches Using SystemVerilog by Janick Bergeron. Can anybody tell me where to get this Ebook? Thanks in advance. Another question of mine, to me, the EDA Books...
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