Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Robin_zhu

  1. R

    sdf back-annotation warning: conditional delay path

    Hi I met warnings on the COND path in sdf file can't be annotated to netlist. all the COND path can't be annotated while others can be annotated. ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (COND ((A===1)&&(C===1)) (IOPATH B Z)) of instance...
  2. R

    how to deal with the problem of multiple clock domain?

    There are some very nice articles on this topic which you can find at synopsys' SolvNet.
  3. R

    What do u mean by design for verification

    DFV is a very fashion concept. I used to attend a synopsys seminar trageted on verification. They advacate SystemVerilog for implementing DFV idea.
  4. R

    VHDL and Verilog which one you use more often?

    we use verilog in our company
  5. R

    Information about High Level Synthesis

    Re: High Level Synthesis Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis
  6. R

    Information about High Level Synthesis

    Re: High Level Synthesis A method for area estimation of data-path in high level synthesis
  7. R

    Information about High Level Synthesis

    Re: High Level Synthesis HLS2.Combined Word-Length Optimization and High-Level Synthesis of Digital Signal Processing Systems
  8. R

    Information about High Level Synthesis

    Re: High Level Synthesis HLS1.Bridging the Domains of High-Level and Logic Synthesis HLS2.Combined Word-Length Optimization and High-Level Synthesis of Digital Signal Processing Systems HLS3.A method for area estimation of data-path in high level synthesis
  9. R

    Information about High Level Synthesis

    Re: High Level Synthesis Hi, i also need some books on high-level synthesis. i used to download some ieee papers.
  10. R

    Looking for books on Verilog PLI

    HI linuxluo! Here is "VERILOG-HDL PLI Reference Manual"
  11. R

    Which language is better Vera or Specman E ?

    Re: vera Versus specman SystemC aims at system design--modeling both hardware and software. Vera mainly targets verification,then. Does anyone here really use these languages in pratical design project?
See more

Part and Inventory Search

Back
Top