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I designed a pll chip and did the post layout simulation. the result gave me 0.5W total power dissipation. The peak power can reach 1 W.
Is that too large to burn the chip after fabrication?
I have no idea. I never taped out before. Please give me some idea. Thanks a million.
The process is...
Can I leave the dummy open? that means dont connect the ends of the dummy transistors? or just connect some ends and leave other ends open?
one more question:
I put dummy resistors surrounded by nwell which connected to VDD. I connect to ends of dummy resistors to VDD but cound't pass the...
I am doing the layout of a differential amplifier and considering put dummy transistors for the input pair which needs good matching.
How to deal with the dummy transistors? leave the Drain, Gate, Source open? I think dummy transistors will share drain or source with the input pairs. how to...
poly resistor layout
Should I put capacitors and resistor in Nwell?
Added after 11 minutes:
one more question:
I use poly to draw the resistor layout, if it is not good useing the minimum ploy width as the resistor width.
Say, is the minumum poly width should be 0.6um. I draw the resistor...
Sorry I didn't make myself clear.
I mean the PSRR performance of resistive load amplifer is good because the resistive load is indepentdant with the supply variation. I know the resistance of the resistor wont change with the supply variation. but why the PSRR will be good?
you see...
When I was reading a book, I read this sentence:
in a differential amplifer, resistive load is independent with supply variation. for example, the input is NMOS and the load is resistor. Why it is indepentdent?
I know the structure of ∑Δ modulator, but why call it sigma and delta? what sigma means and what delta means?
Is that just because plus the reference voltage sometimes and substract reference sometimes?
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