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Recent content by rknmahesh

  1. R

    integer in verilog synthesize to

    Ya I too agree but what if its not a iteration loop lets say a counter incrementing evry posedge of clock
  2. R

    integer in verilog synthesize to

    If not initialized in a iteration loop or even in a iteration loop it should remember its own previous value which infers as a memory. So I think it may be inferred as register only may be... As I also dont know some one help...
  3. R

    integer in verilog synthesize to

    Generally if I declare a variable as integer in verilog.. What hardware element the synthesis tool will take that variable. Thanks in advance
  4. R

    Small doubt regarding verilog

    But as if in the individual blocks can we decrease the power b'coz i need my design to be an ultra-low power design
  5. R

    Small doubt regarding verilog

    I want to design a base band of a system using verilog. It should work at very low power. Whatever I do in verilog how to ensure that it should have lowest power. Or shall I do basic elements in transistor level to ensure that they have low power. Thanks in advance
  6. R

    Low power design in verilog

    Hello, I want to design transistor level design for low power and want to use it in verilog. Is it possible..?
  7. R

    help me to write code for following circuit

    Better know what a carry look ahead do. it calculates carry in advance. U have shown only the sum in the module. u chech again ur question
  8. R

    help me to write code for following circuit

    if u r writing in verilog then CODE: always @ (posedge clk or posedge reset) if (reset==1) si=xi; else si=si+xi;
  9. R

    design of 8085 microprocessor using verilog

    Ya, I know its a big work.. I just want to do some basic small tasks like fibonacci series etc. Can you suggest any sites or books which I can start with the designing. I can do verilog well but i dont know how the microprocessor works along..
  10. R

    design of 8085 microprocessor using verilog

    Hi.. I want to design a 8085 microprocessor using verilog.. I have no idea where to start with.. Can anybody tell the flow i have to follow while designing the modules. Thanks in advance..:)
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