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saif generate
Are you sure you are running with latest version of VCS ?
I have seen that 2006.06-13 doesn't support it, while 2006.07-SP2-7 does. I am not sure in which version they introduced "power" command to ucli prompt.
Re: Timing delays
I meant, design should meet timing in STA tools, otherwise you would anyway see those violations in your simulations ( after annotating SDF generated by same STA tools) and simulation would fail.
Simulator can be any - VCS/NC-verilog/Modelsim etc, All support SDF...
Timing delays
Answering 2nd Question,
- Take a design that meets design,
- backannotate SDF ( generating by STA tools) into simulator
- ensure that standard cell models have all the arcs/checks in specify block
- enable timing checks in simulator ( so that simulator corrupts output as per...
vcs saif
You can use UCLI prompt to dump saif files directly. Make sure you use the latest version of VCS ( 2006.06-SP2-7 or later).
Compile with -debug or -debug_all option,
When running, add -ucli option to commandline, this will give you ucli prompt.
"power -help" will give you info on...
between, when you burned the *.iso image to disc, did you write the disc as data disc or as image ?
As a check, insert this disk in a working computer ( of your friends) after it has booted. Then look at the contents. If you see a single *.iso file, then you haven't burnt the cd correctly. If...
Re: FIFO
Thats because FIFO storage is used as a circular buffer. So it could be while read_pointer is pointing at max location, write_pointer is pointing at 0.
Firstly, what is the design intent ?
So far we are clear that if they are from same source and have a deterministic relationship, we can time them in STA, and make sure that there is no setup/hold violation on the data transfer.
But, if they are not coming from same clock source, and we infer...
Install XP first, in your case its already there.
Then install Linux on a separate partition on harddisk.
If you are picking up any modern linux distribution, like ubuntu/suse/fedora/mandriva etc, it would automatically detect that XP is installed, and would configure the bootloader for...
What is the relationship between waveform of CLK1 and Clk2 ?
Are they coming from same source ? is one a divided version of other ? What is the least separation that can be between edges of CLK1 and CLK2 ? is that deterministic ?
job offers choosing
Before I say more, these are my thoughts, and may or may not be the conventional widom.
Yes Broader range of work,move around in different areas of ASIC design, like frontend design, verification, backend, emulation before you settle on any one of these.
Learn about...
job offers choosing
My opinion goes for job that gives wider exposure. In greed of higher initial pay, one might get stuck into a very limited specialized field. Pay should not be the first consideration atleast in early phase of career. As you build up knowledge, your value will increase...
Re: Delaying the Clock
I don't think inserting buffer is a solution. You can size it to give it exactly T/4 delay, but only at one corner of PVT. But in actual silicon, PVT is going to change. So you won't have exact T/4 delay in a lot of parts of same design.
The right way is to use DLL -...
what is hold time negative
Usually negative hold time is not intentional, but because datapath delay got increased because of Scan mux on D or some other reason like balancing internal delays.
clock and data rate
I am still missing your point.
If we move from 125 Mhz to 25 Mhz, then we definitely need to increase bus width from 8 bits to 40Bits to match the bandwidth.
At any point whether its before serializer/deserializer or after it, the bus width should be such that it gives...
Re: clock and data rate
Can you give some more background on "unequivocal frame synchronisation" ?
I think any integer part of word rate needs to be rouned-off to next higher integer ( ceiling), hence would be higher than what I said.
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